Digital PLL Frequency Control with Extended DCO Lock Range
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Solution Overview
Problem
Conventional digital phase-locked loop (DPLL) circuits have limited lock range due to narrow counter operating frequency, restricting their ability to track phase differences effectively.
Innovation Solution
A DPLL frequency synthesizer with a digitally controlled voltage-controlled oscillator (DCO) and additional feedback loops, including a PVT, ACQ, and TCK registers, along with an adder module to maximize the DCO frequency output range, allowing precise control and polar encoding of digitally modulated signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DPLL circuits use a narrow counter operating frequency range, then the circuit complexity is reduced, but the lock range is limited and phase difference tracking capability is restricted
Solution Approach 1:
The patent segments the frequency control into multiple independent registers (PVT register for coarse control, ACQ register for acquisition, and TCK register for tracking) rather than using a single counter. This segmentation allows each register to operate within optimized frequency ranges, collectively achieving a wide lock range without requiring a single complex high-speed counter
Solution Approach 2:
The patent implements dynamic switching between different registers based on the locking state. During acquisition, the ACQ register is active; during tracking, the TCK register takes over. This dynamic allocation of control functions allows the system to adapt its complexity to operational needs, achieving wide lock range only when necessary
2Adaptability or versatility
If the counter operating frequency is increased to expand lock range, then the phase difference tracking capability is improved, but the circuit complexity and difficulty of detecting and measuring increase
Solution Approach 1:
Different registers are assigned different frequency ranges and control resolutions tailored to their specific functions. The PVT register handles coarse frequency adjustments with lower resolution requirements, while the TCK register handles fine tracking with higher precision. This local optimization of measurement requirements simplifies detection and measurement for each stage
Solution Approach 2:
The patent introduces a frequency divider as an intermediary between the reference clock and the phase comparator. This intermediary reduces the operating frequency at the phase detection stage, making measurements easier while still allowing the DCO to operate at higher frequencies for extended lock range
3Productivity
If additional feedback loops and registers are added to maximize DCO frequency output range, then the frequency modulation capabilities are enhanced, but the device complexity increases
Solution Approach 1:
The multiple registers (PVT, ACQ, TCK) serve multiple functions: frequency setting, phase synchronization, acquisition, and tracking. The feedback loops simultaneously perform frequency correction and phase error reduction. This multi-functionality justifies the added complexity by consolidating what would otherwise require separate circuits
Solution Approach 2:
The patent implements nested feedback structures where the TCK register provides fine tracking within the broader ACQ register range, which itself operates within the PVT register's coarse frequency range. This nested arrangement allows complex frequency modulation capabilities to be built from simpler, hierarchical control stages
Data Source
AI summary
The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.