Digital PLL Pseudo-Random Delay for TDC Dead-Zone Wobble
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face performance degradation due to a 'dead zone' caused by the finite resolution of time-to-digital converters (TDCs), leading to phase wobble, increased jitter, wander, and low-frequency noise, which affects the accuracy of the output phase.
Innovation Solution
Introducing a pseudo-random delay to the input and/or feedback clocks using a multi-bit pseudo-random binary sequence generator and a programmable delay line, which varies the clock edges beyond the TDC's resolution, thereby averaging out noise and reducing wobble.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a TDC with finite resolution is used to determine phase difference, then the device complexity is reduced, but phase wobble and measurement precision deteriorate due to the dead zone effect
Solution Approach 1:
The patent applies dynamics by making the delay line programmable and adjustable. The delay line's delay amount is dynamically varied using a pseudo-random binary sequence generator, allowing the system to escape from the dead zone effect of the TDC. This dynamic adjustment enables the clock edges to be shifted beyond the TDC's resolution limits, thereby reducing phase wobble while maintaining device simplicity.
2Measurement precision
If the TDC resolution is increased to reduce phase wobble, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces a pseudo-random binary sequence generator and programmable delay line as intermediary components between the reference clock and the TDC. These intermediaries manipulate the clock edges to vary the phase difference beyond the TDC's resolution capability, effectively using a low-resolution TDC to achieve high measurement precision without increasing the TDC's complexity.
3Device complexity
If a fixed delay line is used, then device complexity is reduced, but phase accuracy deteriorates due to inability to vary delay beyond TDC resolution
Solution Approach 1:
The patent transforms the fixed delay line into a programmable delay line that can dynamically adjust its delay amount. By controlling the delay line with a pseudo-random binary sequence generator, the system can vary the delay beyond the TDC's resolution, thereby achieving high phase accuracy while keeping the hardware complexity relatively low.
Solution Approach 2:
The patent changes the delay parameter of the delay line dynamically using a pseudo-random binary sequence. This parameter variation allows the system to escape from the dead zone effect and achieve accurate phase measurement without requiring a high-resolution TDC, thus maintaining simplicity while improving precision.
Data Source
AI summary
A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.