Digital Phase-Locked Loop Without Analog Delay Lines
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Solution Overview
Problem
Existing phase-locked loop systems for sub-clock or sub-pixel accurate phase-measurement and phase-generation face challenges with high jitter due to analog components, which are prone to noise and ground bounce, and are difficult to transfer between processes due to temperature and process dependencies.
Innovation Solution
A fully digital circuit arrangement that eliminates the need for a clock multiplier PLL and analog delay lines, using a discrete time oscillator to generate clock signals directly, allowing for higher frequency resolution and easier process scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog components (ring oscillator, delay line) are used for phase generation and measurement, then sub-clock resolution is achieved, but jitter increases due to noise and ground bounce
Solution Approach 1:
The patent replaces the mechanical/analog ring oscillator and delay line with a fully digital phase generation and measurement system. The discrete time oscillator uses digital counters and logic circuits instead of analog oscillating elements, eliminating the inherent noise and ground bounce issues of analog components while maintaining sub-clock resolution through digital time-to-digital conversion.
2Measurement precision
If analog delay line is used for time-to-digital conversion, then process transfer becomes difficult due to temperature and process dependencies
Solution Approach 1:
The patent substitutes the analog delay line with a fully digital implementation using discrete time oscillator and digital counters. This digital architecture eliminates temperature and process dependencies because digital logic circuits have much lower sensitivity to environmental variations compared to analog delay elements, enabling easy process transfer and scaling.
Solution Approach 2:
The patent changes the fundamental operating parameters from analog time delays to digital count values. By measuring time as discrete clock cycles counted by digital counters rather than analog voltage or current delays, the system achieves process independence and enables straightforward parameter adjustment through digital control without requiring physical recalibration.
3Speed
If clock multiplier PLL is used before delay line, then input frequency is sufficient, but additional analog blocks contribute to jitter
Solution Approach 1:
The patent eliminates the clock multiplier PLL by implementing a fully digital frequency synthesis approach. The discrete time oscillator directly generates the required output frequency using digital division and phase selection, removing the need for additional analog frequency multiplication stages that would otherwise contribute to jitter accumulation.
4Measurement precision
If 64-stage delay line is used for reference, then alignment difficulty increases and linearity problems occur
Solution Approach 1:
The patent replaces the complex 64-stage delay line with a much simpler digital counter-based time-to-digital converter. Instead of requiring precise alignment of 64 analog delay stages, the digital implementation uses simple binary counters and logic circuits that are inherently aligned through digital timing signals, dramatically reducing alignment complexity while maintaining or improving linearity.
Data Source
AI summary
In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40′) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50′) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40′), the status signal (dto-status) of at least one register unit (54; 54′) of the digital ramp oscillator unit or discrete time oscillator unit (50; 50′) being fed back as input signal to the phase detector unit (30); and at least one digital-to-time converter unit (60, 62; 60′, 62′) being provided with at least one output signal (dto-co) of the digital ramp oscillator unit or discrete time oscillator unit (50; 50′) and generating at least one output signal (hoi, ho2).