Digital PLL Dithering for Fine Frequency Resolution and Low Spurs
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Solution Overview
Problem
Current cellular phone handsets face challenges in reducing analog/RF board space, which hinders the addition of new features and footprint reduction due to the immaturity of advanced processes, and there is a need for accurate estimation of RF oscillator frequency-modulation gain to improve phase-locked loop performance.
Innovation Solution
The development of an Interpolative All-Digital Phase Locked Loop (iADPLL) with a digitally-controlled oscillator (DCO) using sigma-delta dithering for fine frequency resolution, and a hybrid stochastic gradient algorithm for KDCO inverse calibration, which allows for efficient loop filter operation in the channel frequency domain and reduces reference spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog/RF circuitry is used to provide oscillator functionality, then frequency modulation gain estimation accuracy is improved, but board space occupancy increases and design portability to advanced processes is hindered
Solution Approach 1:
The patent replaces analog/RF oscillator circuitry with a digitally controlled oscillator (DCO) implemented in CMOS logic. The DCO uses digital tuning words to control oscillator frequency, eliminating the need for analog RF components while maintaining frequency modulation functionality. This substitution reduces board space occupancy and enables design portability to advanced CMOS processes while preserving the ability to estimate frequency modulation gain through digital measurement techniques.
Solution Approach 2:
The patent changes the operational parameters of the oscillator from analog voltage control to digital word control. The DCO responds to digital tuning words (TW) that specify frequency values, allowing precise digital control of oscillator parameters. This parameter change enables accurate measurement of frequency modulation gain through digital analysis of the relationship between tuning words and resulting frequencies, while significantly reducing the physical space required for oscillator implementation.
2Area of stationary object
If digital circuitry is used to replace analog RF circuitry, then board space is reduced and design portability is improved, but accurate estimation of frequency modulation gain becomes more difficult
Solution Approach 1:
The patent implements a feedback mechanism where the digital controlled oscillator's output frequency is measured and compared against the input tuning word. By observing the relationship between the digital tuning word and the actual oscillator frequency output, the system can calculate and store the frequency modulation gain (KDCO) value. This feedback loop enables accurate estimation of the gain parameter despite the digital implementation, resolving the measurement difficulty while maintaining the space-saving benefits of digital circuitry.
Solution Approach 2:
The patent substitutes analog measurement techniques with digital measurement and calculation methods. Instead of using analog instruments to measure frequency modulation gain, the system uses digital counters, timing circuits, and computational logic to measure the oscillator period and calculate the gain parameter. This substitution maintains measurement accuracy while being consistent with the digital implementation approach that reduces board space.
3Manufacturing precision
If dithering is applied to the digitally controlled oscillator, then fine frequency resolution is achieved, but spectral contribution in receive bands increases
Solution Approach 1:
The patent applies periodic dithering signals to the DCO tuning word to achieve fine frequency resolution. By adding a small periodic variation to the digital tuning word, the system can effectively resolve frequency steps smaller than the native DCO resolution. The periodic nature of the dither allows the harmful spectral contributions to be predictable and potentially filterable, rather than random and broadband, thus mitigating the interference issue while maintaining fine frequency control capability.
Solution Approach 2:
The patent introduces dithering as an intermediary mechanism between the coarse DCO frequency steps and the desired fine frequency resolution. The dither signal acts as a mediator that fills in the gaps between discrete DCO frequency steps, effectively creating finer frequency granularity. By carefully designing the dither characteristics (amplitude, frequency, waveform), the system achieves fine resolution while controlling the spectral impact on receive bands through the intermediary dithering function.
Data Source
AI summary
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.