Digital PLL Dithering for Integer-Channel Phase Error Reduction
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Solution Overview
Problem
Current cellular phone handsets face challenges in reducing analog/RF board space, which hinders the addition of new features and footprint reduction due to the immaturity of advanced processes, and there is a need for accurate estimation of RF oscillator frequency-modulation gain to improve phase-locked loop performance in digital transceivers.
Innovation Solution
The development of an Interpolative All-Digital Phase Locked Loop (iADPLL) architecture that uses a digitally-controlled oscillator (DCO) with sigma-delta dithering for fine frequency resolution, employing Infinite Impulse Response (IIR) filters and a PI controller, and incorporating a Hybrid Stochastic Gradient algorithm for KDCO inverse calibration, which operates on a channel frequency-derived clock to reduce reference spurs and improve spectral and phase-domain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog/RF circuitry is used to maintain performance, then reliability is improved, but area of stationary object increases
Solution Approach 1:
The patent replaces analog/RF circuitry with digital circuitry implementing a digital phase-locked loop (DPLL) architecture. The DCO (digitally controlled oscillator) and associated digital circuits substitute for traditional analog RF components, enabling footprint reduction while maintaining RF functionality through digital signal processing techniques.
Solution Approach 2:
The patent employs dithering techniques that add controlled random variations to the digital control word of the DCO. This parameter modification allows the system to achieve finer frequency resolution and improve linearity of the DCO gain characteristic, enabling accurate RF performance with digital circuitry.
2Area of stationary object
If digital circuitry is used to reduce board space, then area of stationary object decreases, but manufacturing precision worsens
Solution Approach 1:
The patent implements a feedback mechanism where the DCO gain characteristic is measured and used to adjust the dithering parameters. The system monitors the actual frequency output and compensates for manufacturing variations by adapting the dither signal, thereby achieving accurate frequency control despite process variations in digital circuitry.
Solution Approach 2:
The patent performs preliminary calibration of the DCO gain characteristic during manufacturing or initialization. By pre-characterizing the DCO and storing correction data, the system compensates for manufacturing precision limitations before actual operation, ensuring accurate frequency synthesis.
3Measurement precision
If dithering is applied to improve frequency resolution, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent employs periodic dithering sequences with specific patterns and frequencies optimized for the DCO characteristics. By using periodic rather than purely random dithering, the system achieves frequency resolution improvement while maintaining predictable behavior and reducing the complexity of dither signal generation and processing.
Data Source
AI summary
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.