All-Digital PLL Dithering for TDC Quantization Error
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Solution Overview
Problem
Radio frequency synthesizers using digital phase locked loops face quantization errors due to delays and skews in time to digital converters, leading to incorrect time differences and control signals for digitally controlled oscillators.
Innovation Solution
The implementation of a digital phase lock loop circuit comprising a digitally controlled oscillator, digital processor, phase acquisition circuit, counter, and time to digital converter, with a dithering circuit that adds random noise to the reference clock or feedback signal to distribute energy outside the bandwidth of the phase lock loop, reducing quantization errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a time to digital converter is used to determine time difference between oscillator signal and reference clock, then digital control signal can be generated, but quantization errors occur due to delays and skews
Solution Approach 1:
The patent applies dithering to convert the harmful periodic quantization noise into beneficial white noise. By adding a dither signal to the oscillator output before time-to-digital conversion, the periodic quantization errors are randomized and spread across the frequency spectrum, reducing their impact on control signal accuracy while maintaining measurement precision.
2Measurement precision
If dithering is added to reference clock or feedback signal, then quantization errors are reduced, but device complexity increases
Solution Approach 1:
The patent changes the parameter of the input signal by adding a dither component with specific characteristics (random or pseudo-random sequence with controlled power spectral density). This parameter change transforms the quantization error characteristics without fundamentally altering the time-to-digital converter structure, thus improving measurement precision while limiting complexity increase.
3Reliability
If dithering energy is distributed outside bandwidth, then phase noise performance improves, but loss of energy increases
Solution Approach 1:
The patent applies local quality by shaping the dithering signal's power spectral density to concentrate its energy within the PLL bandwidth where it is useful for reducing quantization errors. The dithering circuit is designed to provide appropriate energy distribution locally within the bandwidth of interest, improving phase noise performance while minimizing energy loss outside the bandwidth through spectral shaping.
Data Source
AI summary
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.