Digital PLL Divider Topology for Wider Loop Bandwidth

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Solution Overview

Problem

Current frequency dividers in wireless communication systems, such as those used in FM receivers, face limitations including asymmetrical duty cycles and insufficient loop bandwidth, which lead to increased phase noise and instability, particularly in high-frequency applications.

Innovation Solution

A phase locked loop (PLL) system with a divide-by-M circuit that includes multiple ⅔ cells and a fixed divide-by-2 cell, combined with dual edge phase-frequency detection and a phase correction circuit, to achieve a nearly perfect 50% duty cycle and increased loop bandwidth, allowing for efficient frequency division and reduced phase noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current frequency dividers are used in high-frequency applications, then frequency division is achieved, but asymmetrical duty cycles and insufficient loop bandwidth lead to increased phase noise and instability

Engineering Contradiction:

Improvephase noise and instabilityVSAvoidfrequency divider structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The frequency divider is segmented into multiple ⅔ cells connected in series, where each cell contributes to the overall division ratio. This segmentation allows for better control of the duty cycle and phase noise characteristics while maintaining the required frequency division function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses a fixed divide-by-2 cell at the output to invert the asymmetrical duty cycle produced by the ⅔ cells, restoring a symmetrical 50% duty cycle. This inversion approach solves the duty cycle distortion problem without requiring complex feedback mechanisms.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If loop bandwidth is increased to reduce phase noise, then phase noise is reduced, but loop stability may be compromised

Engineering Contradiction:

Improvephase noiseVSAvoidloop stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent changes the effective reference frequency parameter by using dual-edge detection, which doubles the reference frequency. This parameter change allows the loop bandwidth to be increased proportionally without compromising stability, as the relative bandwidth with respect to the reference frequency remains appropriate.

Inventive Principle:

Principle #35Parameter changes

3Speed

If dual edge phase-frequency detection is implemented, then loop bandwidth is enhanced, but device complexity increases

Engineering Contradiction:

Improveloop bandwidthVSAvoidphase-frequency detection circuit

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The phase-frequency detector is designed to perform both phase detection and frequency detection functions using the same circuit structure. The dual-edge operation allows the detector to effectively double the reference frequency while maintaining a unified circuit design, avoiding the need for separate detection circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8165260B2Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique

Publication Date: 2012.04.24 TEXAS INSTRUMENTS INC

AI summary

A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.