Digital PLL Calibration for DTC Nonlinearity Correction
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Solution Overview
Problem
Conventional digital phase-locked loops (PLLs) require dedicated hardware such as high-resolution time-to-digital converters (TDCs) and analog-to-digital converters (ADCs), which are costly and inefficient for high precision synchronization clock generation in wireless communications and radar systems.
Innovation Solution
A system and method for estimating and calibrating integrated nonlinearity of digital-to-time converters (DTCs) within PLLs, using a calibration circuit with a code ramp, pre-distortion lookup table, and statistics processor to correct integral nonlinearity, allowing for high precision clock generation without the need for dedicated hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLLs use dedicated high-resolution TDCs and ADCs, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates a digital model (copy) of the DTC's nonlinearity characteristics through calibration and stores it in a lookup table. This digital copy allows the system to compensate for nonlinearity effects without needing additional physical hardware components, thereby maintaining measurement precision while reducing device complexity
Solution Approach 2:
The patent replaces dedicated analog hardware components (TDC, ADC) with digital signal processing techniques. By using digital calibration and lookup tables to correct DTC nonlinearity, the system substitutes complex analog measurement hardware with simpler digital processing, reducing overall device complexity while maintaining precision
2Reliability
If conventional PLLs use dedicated feedback hardware, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a digital feedback mechanism where the PLL output is fed back through the DTC, and the resulting digital signal is used to calibrate and characterize the DTC's nonlinearity. This feedback loop enables the system to continuously refine its understanding of DTC behavior and apply appropriate corrections, maintaining synchronization accuracy without requiring additional dedicated feedback hardware
Solution Approach 2:
The system uses its own existing components (PLL output, DTC, digital signal processor) to perform the calibration and characterization functions. The DTC is calibrated using signals already present in the system, eliminating the need for external calibration equipment or dedicated test hardware, thus reducing device complexity while maintaining reliability
3Device complexity
If DTC integral nonlinearity is not corrected, then device complexity is reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent performs calibration of the DTC during the manufacturing or initialization phase, before the system enters normal operation. The DTC's nonlinearity characteristics are measured and stored in a lookup table in advance. During normal operation, the pre-computed correction values are applied without requiring real-time calibration complexity, thus achieving high precision with minimal operational overhead
Solution Approach 2:
The patent compensates for the DTC's nonlinearity effects in advance by pre-calculating correction values and storing them in a lookup table. This beforehand cushioning approach ensures that when the system operates, the nonlinearity errors are already accounted for and corrected, maintaining manufacturing precision without adding complexity to the real-time operation
Data Source
AI summary
A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.