Digital PLL Duty Cycle Calibration for Low-Noise Synthesizers
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Solution Overview
Problem
Conventional frequency synthesizers using digitally controlled oscillators (DCOs) face high power consumption and introduce substantial noise, while frequency doublers cause duty cycle distortion and deterministic jitter, limiting PLL bandwidth and causing erroneous operations.
Innovation Solution
Implementing a digital phase-locked loop (PLL) with a voltage-controlled oscillator (VCO), multi-modulus divider (MMD), and digitally controlled delay line (DCDL) to reduce power consumption and mitigate duty cycle distortion by extending the time delay range, using a retimer to achieve additional delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a digitally controlled oscillator (DCO) is used in a frequency synthesizer, then frequency generation is achieved, but power consumption increases and noise is introduced
Solution Approach 1:
The patent replaces the digitally controlled oscillator (DCO) with a voltage-controlled oscillator (VCO). This substitution eliminates the need for digital control circuits within the oscillator, thereby reducing power consumption and minimizing noise generation. The VCO is controlled by a voltage signal from the loop filter, which is a cleaner control method compared to direct digital control.
2Speed
If a frequency doubler is used to increase PLL bandwidth, then bandwidth is extended, but duty cycle distortion and deterministic jitter are introduced
Solution Approach 1:
The patent introduces a duty cycle correction (DCC) circuit as an intermediary component between the phase detector and the VCO. This DCC circuit receives the phase detector output and conditions it to eliminate duty cycle distortion before passing it to the VCO. The DCC circuit includes delay elements and logic gates that compensate for the distortion introduced by frequency doubling, thereby maintaining signal integrity while allowing bandwidth extension.
3Manufacturing precision
If duty cycle distortion is corrected using conventional methods, then distortion is reduced, but time delay range is limited
Solution Approach 1:
The patent segments the duty cycle correction function into multiple independent delay elements (e.g., first delay element, second delay element) that can be individually controlled. Each delay element introduces a specific time delay, and their combined effect provides a cumulative delay range that exceeds one period of the VCO output signal. This segmentation allows flexible adjustment of total delay to achieve both accurate duty cycle correction and extended time delay range.
4Measurement precision
If phase synchronization is achieved with small time delays, then phase locking is achieved, but synchronization accuracy is limited
Solution Approach 1:
The patent implements a dynamic time delay adjustment mechanism where the delay elements can be programmatically controlled to provide variable time delays. The system can adaptively select appropriate delay values based on operating conditions, allowing optimization of phase synchronization accuracy. The ability to dynamically adjust delay beyond one period enables fine-tuned phase alignment for improved measurement precision in frequency and phase detection.
Data Source
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AI summary
The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range of time delays, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second range of time delays, and delay the delayed clock signal by the second time delay to generate a feedback clock signal to reduce a difference between the feedback and a reference clock signal.