Digital PLL Duty Cycle Calibration for Low-Noise Synthesizers
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Solution Overview
Problem
Conventional frequency synthesizers using digitally controlled oscillators (DCOs) face high power consumption and introduce substantial noise, while frequency doublers cause duty cycle distortion and deterministic jitter, limiting PLL bandwidth and leading to erroneous operations.
Innovation Solution
Implementing a digital phase-locked loop (PLL) with a voltage-controlled oscillator (VCO), multi-modulus divider (MMD), and digitally controlled delay line (DCDL) to extend time delay ranges, reducing power consumption and mitigating duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a digitally controlled oscillator (DCO) is used in a frequency synthesizer, then frequency generation is achieved, but power consumption increases and noise is introduced
Solution Approach 1:
The patent replaces the digitally controlled oscillator (DCO) with a voltage-controlled oscillator (VCO) in the feedback path of the PLL. This substitution eliminates the need for digital control mechanisms in the oscillator, thereby reducing power consumption and avoiding the noise generation associated with digital switching operations. The VCO is controlled by an analog voltage from the loop filter, which inherently operates with lower power and generates less noise.
2Speed
If frequency doublers are used to generate clock signals, then frequency multiplication is achieved, but duty cycle distortion and deterministic jitter increase
Solution Approach 1:
The patent introduces a duty cycle correction (DCC) circuit as an intermediary component between the frequency doubler and the rest of the PLL system. This DCC circuit actively compensates for the duty cycle distortion and deterministic jitter introduced by the frequency doubler, thereby maintaining signal integrity while still achieving the desired frequency multiplication. The DCC circuit acts as a mediator that corrects the harmful effects of the frequency doubler without eliminating its useful frequency multiplication function.
3Device complexity
If conventional PLL bandwidth is limited, then circuit simplicity is maintained, but phase error correction capability is reduced
Solution Approach 1:
The patent extends the time delay range of the programmable delay element from a single cycle to multiple cycles (e.g., 1 to 16 or 32 cycles). This dimensional extension in the time delay domain allows the PLL to achieve wider effective bandwidth and better phase error correction capability without proportionally increasing circuit complexity. The extended delay range provides additional degrees of freedom for the feedback loop to correct phase errors across a broader frequency spectrum.
Data Source
AI summary
The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range of time delays, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second range of time delays, and delay the delayed clock signal by the second time delay to generate a feedback clock signal to reduce a difference between the feedback and a reference clock signal.