Digital PLL Chirp Generation With Fast FMCW Flyback
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Solution Overview
Problem
Current radar systems using Frequency Modulation Continuous Wave (FMCW) waveforms face challenges in achieving faster chirp sequences and larger bandwidths due to limitations in the response time of the control loop, affecting range and velocity resolution in applications like obstacle detection and autonomous intelligent cruise control.
Innovation Solution
A transceiver system with a digital phase locked loop and a main controller that captures and restores a reference state in configuration registers, allowing for efficient generation and repetition of frequency sequences, thereby reducing the fly-back interval and increasing available bandwidth without the need for a ramp-down sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional control loop is used to generate chirp sequences, then the system can maintain stable operation, but the response time is too slow to achieve faster chirp sequences and larger bandwidths
Solution Approach 1:
The system pre-configures multiple control register states corresponding to different chirp parameters before operation. During runtime, the controller simply switches between pre-configured states using control signals, avoiding real-time calculation delays and enabling faster chirp sequence generation while maintaining stability through predetermined valid states
Solution Approach 2:
The patent implements dynamic switching between different control register states by applying control signals to the digital phase-locked loop. This allows the system to rapidly change chirp parameters (frequency, bandwidth, duration) on-the-fly, achieving faster chirp sequences and larger bandwidths while maintaining control loop stability through structured state transitions
2Power
If the control loop response time is increased to achieve faster chirp sequences, then the bandwidth capability improves, but the fly-back interval increases reducing effective duty cycle
Solution Approach 1:
Control register states are pre-configured with optimal parameters for different bandwidth requirements. The controller switches between these pre-optimized states, allowing immediate transition to high-bandwidth modes without gradual ramping, thus minimizing fly-back interval while maximizing bandwidth capability
Solution Approach 2:
The system changes multiple parameters simultaneously by switching control register states - frequency, bandwidth, and duration are all updated in one operation. This coordinated parameter change allows the system to achieve larger bandwidths without extending the fly-back interval, as all adjustments occur atomically rather than sequentially
Data Source
AI summary
A transceiver includes a frequency modulation continuous wave generator to generate a frequency sequence and a digital phase locked loop to generate a waveform based on the frequency sequence. The digital phase locked loop includes a plurality of control registers. A main controller captures a reference state defined in the plurality of configuration registers prior to the frequency sequence, initiates the frequency sequence, restores the reference state of the configuration registers after completion of the frequency sequence, and repeats the frequency sequence after restoring the reference state.