Digital PLL Acquisition Control for Fast Settling Without Overshoot
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase locked loop (PLL) technologies face challenges in achieving fast settling with reduced frequency overshoot, which can cause operational failures in digital circuits, and current solutions either increase settling time or result in steady-state phase errors.
Innovation Solution
The proposed solution involves a digital phase locked loop (DPLL) design that emulates Type-1 PLL behavior during acquisition by setting the integral gain constant to zero, eliminating frequency overshoot, and uses a proportional-integral filter with additional phase offset signals to drive the phase error to zero, allowing for seamless transitions between target frequencies without interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Type-2 PLL is used to achieve fast settling, then settling speed is improved, but frequency overshoot occurs causing operational failures
Solution Approach 1:
The system dynamically switches between Type-1 and Type-2 PLL modes based on operational requirements. During frequency transitions, it operates in Type-1 mode for overshoot-free settling, then switches to Type-2 mode for steady-state phase error correction, achieving both fast settling and operational reliability
Solution Approach 2:
The invention changes the PLL type parameter from fixed to variable, allowing dynamic reconfiguration between Type-1 and Type-2 modes. This parameter change enables the system to optimize performance characteristics (settling speed vs. overshoot control) based on real-time operational needs
2Reliability
If Type-1 PLL behavior is emulated to eliminate frequency overshoot, then frequency overshoot is reduced, but steady-state phase errors remain
Solution Approach 1:
The system continuously alternates between Type-1 and Type-2 PLL modes in a coordinated sequence. Type-1 mode continuously eliminates overshoot during transitions, while Type-2 mode continuously corrects steady-state phase errors, ensuring both frequency stability and phase precision are maintained throughout operation
Solution Approach 2:
The invention implements feedback control by monitoring phase error and frequency deviation, then dynamically adjusting PLL type accordingly. The system uses feedback from phase detectors and loop filters to determine when to switch between modes, ensuring optimal performance is maintained
3Reliability
If integral gain constant is set to zero to emulate Type-1 behavior, then frequency overshoot is eliminated, but phase error cannot be driven to zero
Solution Approach 1:
The integral gain constant is dynamically adjusted between zero (Type-1 mode for overshoot elimination) and non-zero values (Type-2 mode for phase error correction). This dynamic gain adjustment allows the system to achieve both frequency stability during transitions and zero steady-state phase error
Solution Approach 2:
The invention changes the integral gain parameter from fixed to variable, enabling dynamic reconfiguration between overshoot-free operation (Ki=0) and precise phase tracking (Ki>0). This parameter change resolves the contradiction between frequency stability and phase precision
Data Source
AI summary
Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.