Digital PLL Feedback Bypass for Low-Power Stable Locking
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Solution Overview
Problem
Conventional digital phase lock loop (DPLL) circuits consume high power due to the operation of feedback dividers and sync flip-flops, which are necessary for aligning reference and oscillator clock signals but consume significant power.
Innovation Solution
The DPLL circuit bypasses the feedback divider and sync flip-flop once initial frequency lock is established, using the oscillator clock signal as the feedback signal for phase comparison, and employs a modified phase frequency detector to manage phase noise, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback divider and sync flip-flop are operated to align reference and oscillator clock signals, then lock stability is improved, but power consumption increases
Solution Approach 1:
The patent implements a dual-mode feedback system where the feedback path dynamically switches between two configurations: (1) a high-stability mode using feedback divider and sync flip-flop for initial frequency acquisition and coarse locking, and (2) a low-power mode using a simplified feedback path for fine phase adjustment. This dynamic reconfiguration allows the system to adapt its power consumption and stability characteristics based on the locking stage, resolving the contradiction between maintaining lock stability and reducing power consumption.
Solution Approach 2:
The feedback control process is segmented into distinct phases: frequency acquisition phase where the full feedback path (including divider and sync flip-flop) is active to ensure stability, and phase tracking phase where a simplified feedback path is used to reduce power consumption. This segmentation allows each subsystem to operate optimally in its designated phase, achieving both stability during critical operations and power efficiency during routine operation.
2Measurement precision
If feedback divider is used to divide oscillator clock signal, then frequency alignment is improved, but device complexity increases
Solution Approach 1:
The patent employs a multi-functional feedback switching mechanism that can operate in different configurations: it can use the feedback divider for frequency division when needed, bypass it for direct feedback, or combine both paths. This universal switching structure allows the same circuit to perform multiple functions (frequency alignment, phase comparison, power saving) without requiring separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining frequency alignment precision.
3Measurement precision
If sync flip-flop is used to synchronize clock signals, then phase accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic feedback path that switches between utilizing the sync flip-flop for phase synchronization during frequency acquisition and bypassing it during phase tracking. This dynamic approach allows the system to achieve high phase accuracy when needed while minimizing power consumption during routine operation, effectively resolving the contradiction between phase accuracy and power consumption.
Data Source
AI summary
A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.