Digital PLL Feedback Divider for Wide Bandwidth and Low Jitter
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Solution Overview
Problem
Designing a phase locked loop (PLL) that simultaneously provides a wide bandwidth to reduce internally generated jitter while implementing a fractional-N divider in a low jitter architecture is challenging, as existing solutions must trade off between minimizing jitter and susceptibility to noise.
Innovation Solution
The implementation of a digital PLL with a variable feedback divider that toggles between divider values N and N+1, using a programmable integer divider and a variable delay module to generate a feedback oscillation with reduced jitter, allowing for a wide bandwidth while maintaining low jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the overall bandwidth of the PLL is reduced to filter out jitter energy, then jitter is minimized, but the PLL becomes susceptible to internally generated noise
Solution Approach 1:
The patent replaces the traditional analog charge pump and loop filter with a digital phase detector and digital loop filter. The digital loop filter uses a moving average algorithm to filter jitter from the feedback signal while maintaining wide bandwidth, thereby reducing both jitter and noise susceptibility simultaneously. This substitution of digital processing for analog filtering resolves the contradiction by enabling effective jitter filtering without the bandwidth limitations of analog designs.
2Adaptability or versatility
If a fractional-N divider is used to achieve non-integer division ratios, then flexibility in output frequency is improved, but jitter increases due to constant switching between divider values
Solution Approach 1:
The patent replaces the fractional-N divider with a digital implementation that uses a phase accumulator and modulo operation. The phase accumulator increments by a fractional value each cycle, and the modulo operation generates the divided output without requiring physical switching between integer divider values. This digital approach maintains frequency flexibility while eliminating the jitter caused by constant divider switching.
Solution Approach 2:
The patent implements periodic filtering of the feedback signal using a moving average algorithm in the digital loop filter. This periodic filtering action smooths out the jitter introduced by fractional division while maintaining the desired output frequency, thereby resolving the contradiction between frequency flexibility and jitter reduction.
Data Source
AI summary
A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.