Digital PLL Phase Control Using Shifted Feedback Pulses
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Solution Overview
Problem
Existing PLLs face stringent phase noise requirements and lack programmability to support accurate beamforming and frequency control in 5G systems, particularly at millimeter wave frequencies, where precise phase shifts and frequency adjustments are necessary for efficient wireless communication.
Innovation Solution
A digital phase control method for PLLs that shifts timing pulses in the feedback signal to achieve desired phase shifts without altering the output frequency, using a phase control circuit with a multiplexer and delay line to maintain accurate phase control and frequency programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL feedback signal timing is shifted to achieve desired phase shift, then phase control accuracy is improved, but the frequency divisor stability deteriorates
Solution Approach 1:
The patent applies periodic action by periodically selecting different feedback signal paths through a multiplexer, where each path corresponds to a different delay amount. The phase control circuit periodically switches between multiple delay lines (e.g., 0 delay, 1 cycle delay, 2 cycles delay) in a cyclic manner, achieving average phase shift control while maintaining the integer nature of the frequency divisor at each instant, thus resolving the contradiction between phase accuracy and divisor stability.
2Adaptability or versatility
If the PLL output frequency is changed to support frequency programmability, then adaptability is improved, but phase noise performance deteriorates
Solution Approach 1:
The patent segments the frequency control and phase control functions into independent pathways. Frequency programming is achieved by programming the frequency divisor value, while phase control is achieved separately through the timing shift circuitry. This segmentation allows frequency to be changed without necessarily degrading phase noise, as the phase control mechanism can compensate or the system can be designed to maintain phase noise performance across frequency changes.
3Adaptability or versatility
If the feedback signal timing is shifted to achieve phase shift, then phase control capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the phase control functionality into the existing feedback path of the PLL by integrating a multiplexer and delay lines into the feedback signal route. Instead of adding a separate phase control loop, the phase control is combined with the frequency control path, allowing both functions to share common components like the phase detector and VCO, thus reducing overall system complexity while achieving independent phase and frequency control.
Data Source
Figure 1A~1B
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AI summary
A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.