Digital PLL Clock Recovery With Fixed Sampling and Decimation
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Solution Overview
Problem
Existing digital PLL circuits for optical disc devices face challenges with large-scale analog circuits, high power consumption, and increased loop delay due to wide frequency ranges and limited sampling frequency switching, leading to instability and phase errors during data reproduction.
Innovation Solution
A digital PLL circuit design incorporating an anti-aliasing filter (AAF), an analog-to-digital converter (ADC), and a down converter, where the AAF limits frequency bandwidth and the ADC samples signals at a fixed frequency, with a digital phase tracking unit generating a synchronous clock signal, reducing the need for frequency synthesizers and VCOs, and allowing decimation ratio changes to manage multiplied speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide frequency range is covered to support both inner and outer periphery reproduction in CAV control, then the PLL can handle all disc regions, but the capture frequency range becomes excessively wide (2.4 times ratio), making stable synchronous clock extraction difficult
Solution Approach 1:
The patent applies dynamics by making the sampling frequency adjustable rather than fixed. The sampling frequency is dynamically changed based on the reproduction position (inner or outer periphery) to optimize PLL performance for each region while maintaining overall system adaptability across the entire frequency range.
Solution Approach 2:
The patent changes the sampling frequency parameter according to the reproduction position. By adjusting this key parameter, the system can narrow the effective capture frequency range for each region, improving PLL stability while still covering the full frequency spectrum through parameter adaptation.
2Adaptability or versatility
If frequency synthesizers and VCOs are used to generate sampling clocks for different frequencies, then the PLL can adapt to various multiplied speeds, but the analog circuit scale increases and power consumption rises
Solution Approach 1:
The patent extracts and removes the frequency synthesizer and VCO components from the system. Instead of using these complex analog circuits to generate sampling clocks, the invention uses a fixed-frequency sampling clock combined with digital decimation to achieve multiplied speed adaptation, significantly reducing analog circuit scale and power consumption.
Solution Approach 2:
The patent substitutes analog frequency generation mechanisms (frequency synthesizers and VCOs) with a digital signal processing approach using fixed-frequency sampling and decimation. This replacement eliminates complex analog circuits while maintaining the ability to handle various multiplied speeds through digital processing.
3Device complexity
If the sampling frequency is fixed, then the analog circuit design is simplified, but the PLL cannot effectively handle different multiplied speeds and frequency ranges
Solution Approach 1:
The patent introduces dynamics through the decimation ratio, which is可变 (variable) based on the reproduction position and multiplied speed. While the sampling frequency remains fixed, the decimation ratio adapts to different speed requirements, maintaining system versatility without complicating the analog circuit design.
Solution Approach 2:
The patent introduces the decimation stage as an intermediary between the fixed-frequency sampling and the final output. This intermediary component enables the system to handle different multiplied speeds by adjusting the decimation ratio, effectively bridging the gap between fixed sampling and variable speed requirements.
4Use of energy by stationary object
If analog circuits are minimized and digital processing is used, then power consumption is reduced, but loop delay may increase due to digital processing stages
Solution Approach 1:
The patent removes complex analog circuits (frequency synthesizers, VCOs) that consume significant power. The remaining digital processing stages are optimized to minimize loop delay, achieving low power consumption without excessive time loss through efficient digital signal processing.
Solution Approach 2:
The patent uses digital sampling and processing to create accurate digital representations of the analog signal. This digital copying approach allows for precise signal processing with minimal delay, replacing power-hungry analog circuits while maintaining signal integrity and timing accuracy.
Data Source
AI summary
A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.