Reconfigurable Digital PLL for Fractional Frequency and Phase Control
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Solution Overview
Problem
Existing phase-locked loops (PLLs) are not configurable or reconfigurable, making them difficult to use with flexible circuitry like FPGAs and requiring fixed IC layouts, which limits their application and adaptability to varying frequency ranges, jitter levels, power consumption, and environmental conditions.
Innovation Solution
A reconfigurable, digital phase-locked loop that can be implemented as a circuitry netlist, allowing for customizable IC layouts and compatibility with various oscillators, capable of adjusting frequency and phase in response to temperature, voltage, and fabrication process variations, using a memory-based digital controller and configurable oscillator stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fixed PLL designs are used, then the PLL provides stable frequency generation, but it cannot be reconfigured for different frequency ranges, jitter levels, or power consumption requirements
Solution Approach 1:
The patent implements dynamic reconfigurability by making the PLL circuit parameters adjustable through digital control. The loop filter coefficients, reference frequency divider values, and feedback frequency divider values can be dynamically changed to adapt to different frequency ranges, jitter levels, and power consumption requirements while maintaining stable operation
Solution Approach 2:
The patent changes physical and operational parameters of the PLL to achieve reconfigurability. By modifying loop filter coefficients (Kp, Ki), reference frequency division ratios (Nref), and feedback frequency division ratios (Nfb), the PLL can be reconfigured for different applications without hardware changes, resolving the contradiction between adaptability and complexity
2Adaptability or versatility
If black box PLL designs with fixed IC layout are provided, then the PLL is easy to manufacture, but it cannot be readily inserted into various IC designs without accommodating the fixed floorplan
Solution Approach 1:
The patent segments the PLL design into modular functional blocks (phase detector, loop filter, voltage-controlled oscillator, frequency dividers) that can be independently configured and placed. This modular approach allows the PLL to be inserted into various IC designs with different floorplans while maintaining manufacturing simplicity through standardized module interfaces
Solution Approach 2:
The patent creates a universal PLL core design that can function in multiple IC contexts. By providing a standardized interface and reconfigurable parameters, the same PLL design can be manufactured once and then adapted to various IC floorplans and applications, achieving both layout flexibility and manufacturing simplicity
3Adaptability or versatility
If the PLL is made reconfigurable for multiple parameters, then it can adapt to different frequency ranges and power consumption, but it increases the complexity of control and configuration
Solution Approach 1:
The patent implements feedback mechanisms that automatically adjust PLL parameters based on measured performance. The system monitors frequency accuracy, phase noise, and power consumption, then uses feedback control to optimize loop filter coefficients and division ratios, reducing the complexity of manual configuration while maintaining high adaptability
Data Source
AI summary
A reconfigurable digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator to generate an input signal having a reference frequency. A representative embodiment of the reconfigurable digital phase-locked loop integrated circuit may include a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency; and a second digital phase-locked loop circuit coupled to the first digital phase-locked loop, the second digital phase-locked loop configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase.