Digital PLL Fast Frequency Change for Voltage Droop Response
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Contemporary processors face challenges in quickly reducing frequency to mitigate voltage droops and overheating, requiring a mechanism to slow down frequency faster than voltage droops to reduce the extra voltage guardband.
Innovation Solution
A digital phase-locked loop method that turns off a percentage of active devices in a digitally controlled oscillator and reduces the frequency filter multiplier to quickly adjust processor frequency, allowing for fast recovery and preventing overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processor frequency is reduced using traditional voltage droop mechanisms, then frequency can be slowed down, but the response time is too slow and excessive voltage guardband is required
Solution Approach 1:
The patent implements dynamic frequency adjustment by controlling the digitally controlled oscillator to respond immediately to frequency reduction requests, rather than relying on slow voltage droop mechanisms. The DCO can be programmed to jump to different frequency divisions, enabling rapid frequency changes while maintaining system reliability through controlled operation.
Solution Approach 2:
The patent changes the operational parameters of the phase-locked loop by modifying the DCO control word and frequency filter settings. By adjusting these parameters dynamically, the system achieves fast frequency reduction without requiring voltage changes, thereby improving response speed while maintaining voltage stability.
2Reliability
If voltage guardband is increased to prevent overheating, then processor reliability improves, but power efficiency decreases and performance is reduced
Solution Approach 1:
The patent implements preliminary frequency reduction capability that allows the processor to proactively lower its operating frequency before thermal or voltage issues arise. By having ready-to-execute frequency reduction commands stored in the DCO, the system can respond preemptively to prevent overheating, eliminating the need for excessive voltage guardbands and improving power efficiency.
3Stability of the object's composition
If processor frequency is reduced slowly to maintain stability, then system stability is maintained, but the ability to respond to voltage droops and overheating is insufficient
Solution Approach 1:
The patent segments the frequency control into two distinct paths: a fast path that provides immediate frequency reduction by directly modifying the DCO control word, and a slow path that maintains normal phase-locked loop operation for stability. This segmentation allows the system to achieve both rapid response and stability by selecting the appropriate path based on system conditions.
Data Source
AI summary
According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.