Two-Step Digital PLL Locking for Large Frequency Offsets
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Solution Overview
Problem
Existing digital phase locked loops (ADPLLs) face challenges in achieving quick response and long-term stability, especially at high clock speeds, due to limitations in locking frequency differences and correcting phase errors, which affects their performance in applications like gigabit Ethernet systems.
Innovation Solution
A phase locked loop with a digitally controlled oscillator (DCO) and a phase frequency detector (PFD) that operates in a two-step procedure, initially using frequency detection mode for stepwise frequency adjustment and then switching to phase detection mode to correct phase errors, allowing synchronization even with large frequency differences, and incorporating a pattern shift stage to compensate for frequency deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional digital phase locked loop uses only phase detection, then the circuit structure is simple, but it cannot synchronize when the frequency difference between feedback clock and reference clock is too large
Solution Approach 1:
The phase frequency detector is segmented into two functional modules: a frequency detection module that handles large frequency differences by counting clock edges, and a phase detection module that handles fine phase alignment. This segmentation allows the system to handle both coarse frequency synchronization and fine phase adjustment, resolving the contradiction between handling large frequency differences and maintaining circuit simplicity.
Solution Approach 2:
The system dynamically switches between frequency detection mode and phase detection mode based on the frequency difference magnitude. When the frequency difference is large, the frequency detection module is activated; when the frequency difference becomes small, the phase detection module takes over. This dynamic operation enables the circuit to adapt to different synchronization stages, achieving both broad adaptability and operational efficiency.
2Measurement precision
If the phase detection mechanism has limited resolution (one period or less of reference clock), then the circuit is simple, but it cannot correct phase error when frequency difference is large
Solution Approach 1:
The frequency detection module acts as an intermediary that bridges the gap between large frequency differences and the limited resolution of the phase detection module. By first reducing the frequency difference through frequency detection and edge counting, the system prepares the signals for accurate phase measurement, enabling the phase detector to work within its optimal resolution range while the overall system handles large frequency variations.
3Speed
If analog circuits are used for clock generation, then the circuit can operate at high frequencies, but the circuit drifts with aging and temperature
Solution Approach 1:
The invention replaces analog clock generation circuits with a digitally controlled oscillator (DCO) that is controlled by digital signals from the phase frequency detector. This substitution of digital control for analog generation eliminates the drift problems associated with analog circuits while maintaining the ability to operate at high clock frequencies required for gigabit Ethernet systems.
4Stability of the object's composition
If digital circuits are used to avoid drift, then the circuit is stable against aging and temperature, but the response time (locking speed) is too slow
Solution Approach 1:
The frequency detection module uses periodic edge counting of the reference clock and feedback clock to determine frequency differences. By counting edges over multiple reference clock periods, the system accumulates frequency difference information and generates correction signals that drive the DCO toward synchronization. This periodic counting mechanism enables digital circuits to achieve both stability and acceptable locking speed.
Data Source
AI summary
A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.