Digital PLL Gear Shifting for Stable Loop Gain Changes
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Solution Overview
Problem
Current cellular phone handsets face design challenges due to the immaturity of advanced processes for analog/RF components, which occupy a significant portion of board space and hinder the addition of features and reduction of footprint, despite advancements in digital designs.
Innovation Solution
The development of an Interpolative All-Digital Phase Locked Loop (iADPLL) architecture that uses a digitally-controlled oscillator (DCO) with sigma-delta dithering for fine frequency resolution, implementing loop control circuitry with Infinite Impulse Response (IIR) filters and a digital Proportional-integral (PI) controller, and employing resamplers to operate on an RF-derived variable clock domain, reducing reference spurs and improving spectral and phase-domain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If analog/RF circuitry is used in traditional handsets, then RF functionality is achieved, but board space is significantly occupied and feature integration is hindered
Solution Approach 1:
The patent replaces traditional analog/RF circuitry with an all-digital RF processor architecture. The digital RF processor uses digital signal processing techniques to perform functions previously requiring analog components, including frequency synthesis, modulation, and demodulation. This substitution dramatically reduces board space occupation while enabling easier integration of multiple RF features through software-defined functionality.
2Area of moving object
If digital RF processor architecture is implemented, then board space is reduced and feature integration is enabled, but accurate estimation of RF oscillator modulation gain becomes critical
Solution Approach 1:
The patent implements a feedback mechanism where the digital RF processor continuously monitors and measures the actual modulation gain of the RF oscillator. By comparing the expected gain with the measured gain, the system dynamically adjusts digital control parameters to compensate for variations. This feedback approach ensures accurate modulation gain estimation is achieved through measurement and correction rather than relying solely on theoretical calculations.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting digital control words and tuning parameters based on measured oscillator characteristics. The system varies frequency control words, modulation depth parameters, and gain compensation factors to optimize performance across different operating conditions. This parameter adaptation allows the digital RF processor to maintain accurate modulation gain estimation despite process variations, temperature changes, and aging effects.
3Reliability
If all-digital phase locked loop is used, then spectral performance is improved and reference spurs are reduced, but loop control complexity increases
Solution Approach 1:
The patent implements a universal digital loop filter that serves multiple functions within the all-digital phase locked loop. This single digital filter structure performs phase error correction, frequency adjustment, and spectral shaping simultaneously. By consolidating these functions into one multi-functional digital block, the patent achieves improved spectral performance and reduced reference spurs while avoiding the need for separate analog filter circuits, thereby managing complexity through functional integration rather than proliferation of components.
Data Source
AI summary
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—α) and an integral loop gain control having a programmable loop gain coefficient (rho—ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.