Digital Low-Frequency PLL Circuit for HDL Clock Synchronization
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Solution Overview
Problem
Current high-density logic devices lack low-frequency phase-locked loop functionality, which is necessary for applications involving low-frequency operations such as 50-60 Hz, and rely on external components or high-frequency PLLs.
Innovation Solution
A digital low-frequency phase-locked loop system is integrated into high-density logic devices, utilizing internal digital logic to perform the PLL function without external components, comprising a digital logic input-output module, instant lock module, high-speed count comparator, and pulse generators to achieve low-frequency PLL operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external components or high-frequency PLLs are used in HDL devices, then high-frequency PLL functionality is achieved, but low-frequency PLL functionality is lost
Solution Approach 1:
The patent merges the low-frequency PLL functionality directly into the HDL device by integrating a counter, comparator, and control logic units that work together to generate low-frequency output signals (50-60 Hz) from high-frequency clock signals, eliminating the need for external components
Solution Approach 2:
The patent replaces traditional external PLL components with a digital logic implementation using counter units and comparator units that operate entirely within the HDL device, substituting external hardware with internal digital circuitry
2Speed
If high-frequency PLLs are used, then high-frequency operation is achieved, but low-frequency operation (50-60 Hz) is not possible
Solution Approach 1:
The patent implements dynamic frequency scaling by using a counter unit that counts high-frequency clock cycles and a comparator unit that generates output pulses at low frequencies (50-60 Hz) based on the counted value, allowing the system to dynamically adapt between high-frequency input and low-frequency output
Solution Approach 2:
The patent changes the frequency parameter by using a division ratio mechanism where the counter counts a specific number of high-frequency clock cycles before generating one low-frequency output pulse, effectively transforming the frequency parameter from high to low range
3Adaptability or versatility
If external components are used for low-frequency PLL, then low-frequency functionality is achieved, but device footprint increases
Solution Approach 1:
The patent nests the low-frequency PLL functionality within the existing HDL device architecture by integrating the counter unit, comparator unit, and control logic into the device's internal logic structure, allowing the low-frequency capability to be embedded without additional external components
Data Source
AI summary
A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse. The HDL device has a digital low-frequency PLL function without the use of external components.