Digital PLL Clock Holdover Using DCO Sigma-Delta Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital clock systems require external components like filters and comparators, increasing cost and complexity, and struggle to maintain accuracy during holdover events without a stable reference input clock.
Innovation Solution
A digitally-controlled oscillator (DCO) with a sigma-delta modulator, adder, and multi-modulus divider, along with a digital phase/frequency detector and buffer, generates a stable clock signal using a stable source clock, allowing for persistent operation during holdover events with reduced external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a DDS+DAC implementation is used to generate a digital clock, then the clock can be tuned digitally, but external filters and comparators are required which increase cost and complexity
Solution Approach 1:
The patent merges the DDS, DAC, filter, and comparator functions into a single integrated DCO circuit. The DCO generates digital clock signals directly with programmable frequency and phase, eliminating the need for external filters and comparators while maintaining digital tuning capability through a control register.
Solution Approach 2:
The DCO circuit performs multiple functions: it acts as a digital oscillator, a filter, and a comparator simultaneously. The single circuit can generate clock signals, filter harmonics, and provide clean digital outputs, replacing multiple separate components with one universal device.
2Manufacturing precision
If external filters are provided to remove harmonics at the DAC output, then signal quality is improved, but the filter cannot be fabricated within the integrated circuit increasing cost and complexity
Solution Approach 1:
The filter function is merged into the DCO circuit itself. The circuit generates the clock signal and simultaneously filters harmonics through its internal design, eliminating the need for external filter components while maintaining signal quality.
3Productivity
If a DDS+DAC design is used with external components, then clock generation is achieved, but additional space and cost are incurred for extra components
Solution Approach 1:
All clock generation functions including DDS, DAC, filtering, and comparison are merged into a single DCO integrated circuit. This consolidation maintains full clock generation capability while eliminating the space and cost associated with multiple separate components.
Solution Approach 2:
The DCO circuit serves as a universal component that performs oscillation, digital tuning, filtering, and signal conditioning in one device, replacing what would otherwise require multiple specialized components.
4Reliability
If the DPLL operates in holdover mode without reference input clock, then operation continues, but frequency accuracy drifts over time
Solution Approach 1:
The DCO pre-loads frequency and phase data into its control register before holdover mode begins. This preliminary action allows the circuit to maintain accurate clock generation using stored reference data even when the reference clock is unavailable, preventing frequency drift during holdover operation.
Data Source
AI summary
A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).