Digital PLL Clock Generator With Holdover Power Saving
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Solution Overview
Problem
Existing digital PLL circuits face challenges in reducing current consumption without compromising frequency accuracy, as existing methods either focus on overall device reduction or are specific to digital signal processing, not adequately addressing PLL circuit current consumption alone.
Innovation Solution
A digital PLL circuit design incorporating a time-to-digital converter, digital loop filter, digitally controlled oscillator, data holder, and data controller that selectively halts or operates components based on differential data storage and transmission, allowing for reduced current consumption while maintaining frequency accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the digital PLL circuit components are continuously operated to maintain frequency accuracy, then the frequency accuracy is preserved, but the current consumption increases
Solution Approach 1:
The patent implements dynamic operation modes where the digital PLL circuit can switch between normal operation mode (all components active for high frequency accuracy) and low power operation mode (data holder iteratively outputs held data while T2D and DLF are halted, reducing current consumption). This dynamic adaptability resolves the contradiction by allowing the system to optimize between accuracy and power consumption based on operational requirements.
Solution Approach 2:
The patent employs periodic updating of data in the data holder at predetermined intervals. During low power mode, the data holder iteratively outputs the held second digital data periodically to the DCO, maintaining frequency control while the power-intensive T2D and DLF components remain halted. This periodic action ensures frequency accuracy is maintained over time while significantly reducing average current consumption.
2Use of energy by moving object
If the processing speed is decreased to reduce current consumption, then the current consumption is reduced, but the frequency control responsiveness deteriorates
Solution Approach 1:
The data holder pre-stores multiple sets of second digital data output from the DLF in advance. When in low power operation mode, the data holder iteratively outputs these pre-held data sets to the DCO without requiring real-time processing from the T2D and DLF. This preliminary action allows the system to maintain responsive frequency control using pre-computed data while the processing components are halted, thus reducing current consumption without sacrificing responsiveness.
3Use of energy by moving object
If the digital PLL circuit is isolated or halted to reduce current consumption, then the current consumption is reduced, but the frequency control capability is lost
Solution Approach 1:
The patent segments the digital PLL circuit into distinct functional blocks: T2D (time-to-digital converter), DLF (digital loop filter), DCO (digitally controlled oscillator), and data holder. The control unit can selectively halt the power-intensive T2D and DLF segments while keeping the DCO and data holder operational. This segmentation allows current consumption to be reduced by isolating specific components while maintaining the essential frequency control capability through the DCO and pre-held data, resolving the contradiction between power reduction and functionality preservation.
Data Source
AI summary
A circuit according to the present invention includes: an oscillator; an divider; a time-to-digital converter comparing the phase and frequency of a reference clock signal REF from the divider with an internal clock signal and outputting digital data D1 based on the comparison results; a digital loop filter receiving the D1 and outputting digital data W1; a data holder holding the W1 from the filter in time series manner; a switch selecting either digital data W2 from the holder or the W1 and outputting the selected data as digital data W3; a digitally controlled oscillator with oscillation frequency controlled based on the W3; and a data controller switching input data of the switch, and starting/halting the operation of the oscillator, the divider, the converter and the filter. Current consumption by the digital PLL circuit can be reduced.