Digital PLL Carrier Recovery with Integrator Preload
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Solution Overview
Problem
Carrier recovery loops in communications systems face increased acquisition time or feasibility issues when operating outside the lock range due to pipeline delays, which are often unchangeable, leading to unpredictable loop behavior or false-lock conditions.
Innovation Solution
A digital phase locked loop (PLL) is operated in an open-loop mode to determine a carrier frequency offset estimate based on a phase error signal, which is then pre-loaded into the integrator to facilitate a transition to closed-loop mode, reducing acquisition time with minimal hardware and software overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the loop gain is increased to combat incorrect bias in the error estimator, then the reliability of carrier recovery is improved, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-loading the integrator with an estimated carrier frequency offset value before the normal closed-loop operation begins. This preliminary estimation and loading step prepares the system in advance, allowing the loop to start from a corrected state rather than requiring high loop gain to overcome pipeline delays, thus improving reliability without proportionally increasing complexity
2Reliability
If sub-dividing the carrier frequency offset range is implemented to reduce effective offset, then the acquisition feasibility is improved, but the acquisition time increases
Solution Approach 1:
The patent performs preliminary action by estimating the carrier frequency offset and pre-loading the integrator before closed-loop operation. This advance preparation eliminates the need for time-consuming sub-dividing steps, as the system directly starts from a corrected state, thereby maintaining acquisition feasibility while significantly reducing acquisition time
Solution Approach 2:
The patent applies skipping by bypassing the traditional multi-step acquisition process including sub-dividing. Instead, it rushes through the acquisition by directly estimating the offset and pre-loading the integrator, then immediately transitioning to closed-loop mode, thus eliminating unnecessary intermediate steps and reducing overall acquisition time
3Loss of time
If pipeline delay is reduced to eliminate harmful effects, then the acquisition time is reduced, but the device complexity increases due to architectural changes
Solution Approach 1:
The patent introduces an intermediary approach by adding a carrier frequency offset estimation mechanism that operates in parallel with the existing PLL architecture. This intermediary estimation block provides corrected offset values without requiring fundamental architectural changes to the pipeline structure, thus reducing acquisition time while minimizing increases in device complexity
Data Source
AI summary
A receiver includes a digital phase locked loop (PLL) for performing carrier recovery. The digital PLL further includes a phase error estimator driven by hard decisions and an integrator, which accumulates a phase error signal provided by the phase error estimator. To reduce the acquisition time, the digital PLL is run in an open-loop mode during which an estimate of the carrier frequency offset is determined as a function of the phase error signal. After the estimate of the carrier frequency offset is determined, the integrator is pre-loaded with the determined estimate and the digital PLL is run in a closed-loop mode.