Digital PLL Integrator Using Sigma-Delta Decimation for Compact Phase Lock
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Solution Overview
Problem
Conventional phase-locked loop systems face challenges in achieving phase lock due to high or low reference frequencies, requiring large capacitance for loop filters, which is difficult to integrate in modern IC technologies, and result in high power dissipation and large size.
Innovation Solution
The implementation of a phase-locked loop circuit using a digital phase detector with a continuous-time sigma-delta modulator as a decimator and down-sampler, eliminating the need for external components and allowing for low power dissipation and compact size, suitable for high integration in IC technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional analog phase-locked loop uses a large capacitance for the loop filter integrator, then the phase lock capability is improved, but the device size and integration difficulty increase significantly
Solution Approach 1:
The patent replaces the conventional analog integrator circuit with a digital accumulator that performs integration through digital counting operations. The digital domain substitution eliminates the need for large physical capacitors while maintaining the phase accumulation function, thereby reducing device size and enabling better integration.
Solution Approach 2:
The patent changes the operating parameters by using a high-frequency clock signal (e.g., 156.25 MHz) to drive the digital accumulator, allowing the use of much smaller timing components compared to conventional analog circuits. This parameter change enables compact implementation while achieving the required phase measurement resolution.
2Measurement precision
If a conventional phase-locked loop system uses high reference frequencies, then the measurement precision is improved, but the power dissipation increases
Solution Approach 1:
The patent employs periodic sampling of the phase difference signal at a high-frequency clock rate, accumulating phase information over multiple cycles. This periodic action allows precise phase measurement to be achieved through time-averaging in the digital domain, reducing the instantaneous power requirements compared to continuous analog operation at high frequencies.
Solution Approach 2:
The patent uses digital signal copying and processing techniques where the phase information is captured, stored, and processed in the digital domain rather than requiring continuous high-power analog signal processing. This copying approach enables precise measurement with lower power consumption by separating the high-frequency sampling function from the low-power processing function.
3Reliability
If a conventional system uses external components for the integrator with compensating zero, then the phase lock performance is improved, but the ease of manufacture and integration are worsened
Solution Approach 1:
The patent merges the functions of the loop filter, integrator, and compensating zero network into a single digital processing block implemented in integrated circuit form. By combining these previously separate analog components into one digital module, the patent achieves the required phase lock performance while enabling complete integration without external components.
Solution Approach 2:
The patent substitutes the external analog integrator circuit with an internal digital accumulator implemented in semiconductor logic. This substitution eliminates the need for external capacitors and resistors, allowing the entire phase-locked loop to be manufactured as an integrated circuit, thereby dramatically improving ease of manufacture and integration.
Data Source
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Figure 4A
AI summary
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.