Digital PLL Jitter Correction for ADC and DAC Sampling
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Solution Overview
Problem
Non-idealities in phased locked loop (PLL) circuits, such as clock jitter, adversely affect the signal-to-noise ratio of data converters like ADCs and DACs, leading to performance degradation.
Innovation Solution
Incorporating a digital phase lock loop (DPLL) circuit, slope calculation circuit, sampling error circuit, and summing circuit to generate and adjust digital output signals, mitigating sampling errors by calculating and correcting for timing errors in the sampling clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL circuit is used to provide timing signals for data converters, then timing synchronization is achieved, but clock jitter degrades the signal-to-noise ratio
Solution Approach 1:
The patent calculates the slope of the input signal in advance and uses this pre-calculated slope information to predict and correct sampling errors before they occur. The slope calculation circuit computes the derivative of the input signal, and this information is stored and used by the error correction circuit to compensate for timing jitter effects on future samples.
Solution Approach 2:
The patent implements a feedback mechanism where the actual sampling clock signal is monitored, timing errors are detected by comparing expected vs. actual sampling instants, and correction signals are fed back to adjust subsequent sampling operations. This closed-loop approach continuously reduces the impact of clock jitter on conversion accuracy.
2Speed
If sampling is performed using a PLL-generated clock signal, then timing control is improved, but sampling errors due to jitter increase
Solution Approach 1:
The system pre-calculates the slope of the input signal and stores this information for later use in error correction. By having the slope information ready before sampling occurs, the system can quickly compute timing error effects without adding latency to the critical sampling path.
Solution Approach 2:
The patent introduces an intermediate error correction signal that mediates between the raw PLL clock signal and the final sampling operation. This correction signal, derived from slope information and timing error detection, acts as a buffer that translates timing jitter into compensatable voltage errors that can be subtracted from the final conversion result.
3Ease of operation
If clock jitter is present in the PLL circuit, then timing signals are provided, but data converter performance degrades
Solution Approach 1:
The system continuously monitors the timing signals from the PLL, detects deviations from expected timing, and feeds back correction information to compensate for jitter effects. This feedback loop maintains data converter accuracy despite the presence of clock jitter by dynamically adjusting for timing variations.
Solution Approach 2:
The patent replaces direct hardware timing correction mechanisms with a software/digital processing approach. Instead of using complex jitter-cleaner circuits or multiple PLLs, the system uses digital slope calculation and mathematical error compensation to achieve jitter mitigation, substituting mechanical/electrical correction with computational methods.
Data Source
AI summary
This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.