Digital PLL Jitter Detection Using Input-Output Clock Comparison
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Solution Overview
Problem
Existing jitter detection circuits in phase locked loop (PLL) circuits suffer from low accuracy due to manufacturing fluctuations in the phase comparator and threshold voltage, leading to inadequate detection of jitter exceeding permissible values.
Innovation Solution
A digital jitter detection circuit that compares the frequency difference between input and output clocks, outputting an anomaly signal when the frequency difference is outside a predetermined range, utilizing a digital comparison circuit with a counter and comparator to accurately determine jitter levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog phase comparator and analog comparator are used for jitter detection, then the circuit can detect phase difference, but the detection accuracy is low due to manufacturing fluctuations in threshold voltage
Solution Approach 1:
The patent replaces the analog comparison system with a digital comparison system. Specifically, it substitutes the analog phase comparator and analog comparator with digital circuits including a phase-to-digital converter, counter, and digital comparator. This substitution eliminates the threshold voltage fluctuation problem inherent in analog circuits, as digital circuits are not affected by such analog parameter variations, thereby significantly improving jitter detection accuracy
Solution Approach 2:
The patent changes the operating parameters from analog domain to digital domain. By converting the phase difference measurement into a digital count value through a phase-to-digital converter and counter, the system transforms continuous analog parameters into discrete digital parameters. This parameter transformation makes the measurement immune to analog manufacturing variations and enables high-precision jitter detection
2Measurement precision
If a digital comparison circuit is used for frequency comparison, then the detection accuracy is high, but the circuit complexity increases
Solution Approach 1:
The patent employs digital circuits to replace complex analog comparison mechanisms. The digital implementation using counters and digital comparators simplifies the overall circuit architecture while maintaining high detection accuracy, as digital logic operations are inherently more robust and easier to implement with standard integrated circuits
Solution Approach 2:
The digital comparison circuit automatically performs frequency difference detection through programmed logic operations. The counter automatically accumulates clock cycles, and the digital comparator automatically compares the accumulated value against reference values, eliminating the need for manual calibration or adjustment that would increase operational complexity
Data Source
AI summary
There is provided a jitter detection circuit of a phase locked loop circuit, comprising a comparison circuit. The comparison circuit compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit. When it is determined that the frequency difference between the input clock and the output clock is outside a predetermined range, the comparison circuit outputs a first anomaly signal. The comparison circuit is constituted as a digital circuit.