Digital PLL Loop Filter Tuning for Low-Jitter Phase Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase locked loops (PLLs) face challenges in achieving low jitter characteristics, particularly in high-speed interfaces like PCIe, due to noise and quantization errors from limited resolution in time-to-digital converters (TDCs), which affect the accuracy of phase difference detection and frequency control.
Innovation Solution
A digital phase locked loop system that includes a digitally controlled oscillator (DCO), a divider, a TDC, and a digital loop filter with a gain/duty control circuit to adjust gain and duty cycle based on error signals, filtering noise and reducing RMS jitter by offsetting quantization errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital phase locked loop uses a time-to-digital converter (TDC) with limited resolution for phase difference detection, then the device complexity is reduced and area is saved, but quantization errors increase and measurement precision deteriorates
Solution Approach 1:
The patent introduces a digital loop filter as an intermediary component between the TDC and the DCO. This filter processes the error signal from the TDC, applying gain control and duty cycle adjustment to reduce quantization errors before the signal reaches the frequency control input. The filter acts as a mediator that compensates for the limited resolution of the TDC without requiring a higher-resolution converter.
Solution Approach 2:
The patent dynamically adjusts the gain and duty cycle parameters of the digital loop filter based on the error signal characteristics. By changing these parameters adaptively, the system optimizes the filtering effect to minimize quantization errors while maintaining stable operation. This parameter adjustment allows the system to achieve better measurement precision without increasing TDC resolution.
2Device complexity
If the digital loop filter uses fixed gain and duty cycle, then the device complexity is reduced, but the ability to reduce jitter and adapt to different conditions is limited
Solution Approach 1:
The patent implements dynamic gain and duty cycle control in the digital loop filter. Instead of fixed parameters, the gain and duty cycle are adjusted adaptively based on the error signal and system operating conditions. This dynamic adjustment enables the filter to optimize jitter reduction performance across different operating scenarios while maintaining a relatively simple device structure.
Solution Approach 2:
The patent employs feedback mechanisms where the error signal from the TDC is fed back to the digital loop filter, which then adjusts its gain and duty cycle parameters accordingly. This closed-loop feedback allows the system to automatically adapt to changing conditions and optimize jitter reduction without requiring complex external control circuitry.
3Measurement precision
If noise filtering is increased in the digital loop filter, then measurement precision and jitter reduction improve, but the response speed of frequency control deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of filter characteristics through gain and duty cycle control. The filter can adapt its noise rejection capability and response speed based on operating conditions. During transient states, the filter allows faster response by adjusting gain higher, while during steady-state operation, it increases noise filtering by adjusting duty cycle, thus resolving the trade-off between filtering and response speed.
Solution Approach 2:
The patent changes the operational parameters of the digital loop filter (gain and duty cycle) based on the system state. By dynamically modifying these parameters, the filter can optimize the balance between noise filtering effectiveness and response speed, allowing strong filtering when needed while maintaining fast response during transitions.
Data Source
AI summary
A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.