Digital PLL Lock Indicator Using Cascaded Filters for Fast Precision
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Solution Overview
Problem
Conventional clock quality characterization techniques trade off speed of detection with resolution of error detection, failing to accurately monitor frequency and phase lock conditions in clock signals due to limitations in existing technologies.
Innovation Solution
The implementation of a frequency monitoring circuit with cascaded moving average filters and error detection circuits that compare differences between filter stages to determine frequency and phase offset errors, allowing for fast and accurate detection of frequency and phase loss of lock conditions using a combination of fast, medium, and slow threshold values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock quality characterization techniques are used, then detection speed is improved, but measurement precision deteriorates
Solution Approach 1:
The frequency monitoring circuit is divided into multiple cascaded filter stages (first, second, and third stages) with different time constants. Each stage processes frequency offset errors at different time scales, allowing simultaneous fast detection and high precision measurement without trade-off. The segmentation of detection functions across multiple stages resolves the contradiction between speed and precision.
Solution Approach 2:
The patent introduces a multi-dimensional detection approach by using cascaded filters with different time constants (fast, medium, slow). This adds a temporal dimension to the detection system, where each dimension operates at a different speed but contributes to overall measurement precision. The multi-dimensional frequency offset error detection allows the system to achieve both fast detection and high resolution simultaneously.
2Device complexity
If single-stage filtering is used, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
Instead of using a single complex high-order filter, the patent segments the filtering function into multiple cascaded first-order or second-order filters with different time constants. This segmentation approach achieves the same or better measurement precision while keeping each individual filter stage simple and the overall device complexity manageable.
Solution Approach 2:
The cascaded filter stages operate dynamically with different time constants optimized for different detection scenarios. The fast stage responds quickly to sudden frequency changes, while slower stages provide precise steady-state measurements. This dynamic multi-stage approach achieves high precision without requiring an overly complex static filter design.
3Measurement precision
If multi-stage cascaded filters are used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The complex filtering requirement is segmented into multiple simpler cascaded stages, each with a specific time constant. This segmentation allows the use of simple first-order or second-order filters instead of a single complex high-order filter, thereby improving measurement precision while keeping device complexity distributed and manageable across stages.
Solution Approach 2:
Each cascaded filter stage serves multiple functions: it acts as a frequency offset detector, a noise filter, and a basis for threshold comparison. This multi-functionality reduces the need for additional dedicated circuits, thereby improving measurement precision without proportionally increasing device complexity.
4Speed
If fast threshold comparison is used, then detection speed is improved, but measurement precision deteriorates
Solution Approach 1:
The threshold comparison function is segmented across multiple stages with different time constants. Fast threshold comparisons are performed on the first stage output for quick detection, while slower stages provide refined measurements. This segmentation allows the system to achieve both fast detection speed and high measurement precision simultaneously by operating at different temporal resolutions.
Solution Approach 2:
The threshold comparison operation is made dynamic by applying it at different stages with different time constants. The fast stage provides rapid initial detection, while subsequent stages refine the measurement with higher precision. This dynamic multi-stage threshold comparison resolves the contradiction between speed and precision.
Data Source
AI summary
A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.