All-Digital PLL Lock-State Gating for Lower Power and Spurs
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Solution Overview
Problem
Existing all-digital phase-locked loop (ADPLL) architectures face challenges with high power consumption, noise, spurs, complexity, and die area, particularly in mobile telecommunications where transceivers require reduced current consumption and improved linearity.
Innovation Solution
The ADPLL architecture leverages deep-submicron MOSFET technology to reduce complexity, noise, and power consumption by separating integer and fractional phase calculations, turning off circuitry when locked, and utilizing a compact design with a time-to-digital converter (TDC) for high-resolution phase error detection, and a compensator block for modulation compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If prior-art all-digital PLL architecture is used, then digital signal manipulation is enabled with high density integration, but power consumption increases due to large transistor current leakage
Solution Approach 1:
The phase detector is segmented into two separate paths: an integer path using digital counters and a fractional path using a time-to-digital converter (TDC). This segmentation allows each path to be optimized independently, reducing overall power consumption while maintaining high density integration capabilities.
Solution Approach 2:
The circuit employs periodic action by turning off the integer path circuitry when the PLL is locked, activating it only during frequency acquisition. This periodic operation significantly reduces average power consumption while maintaining the benefits of high density integration when needed.
2Manufacturing precision
If more digital circuitry is added for fine device matching and high speed, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The circuit is divided into distinct integer and fractional paths with specialized components for each. The integer path uses simple counters while the fractional path uses a TDC, allowing fine device matching in each segment without requiring complex interaction between them, thus managing overall complexity.
Solution Approach 2:
The fractional phase detection function is extracted and implemented separately using a TDC circuit, removing the complexity of implementing fine phase matching within the integer digital counter path. This extraction allows each subsystem to be optimized independently.
3Speed
If high speed transistors are used for deep-submicron technology, then processing speed improves, but noise and spurs increase
Solution Approach 1:
By segmenting the phase detection into integer and fractional paths, the circuit can use high-speed transistors in the fractional TDC path where they provide maximum benefit, while the integer path can use lower-speed, lower-noise digital counters, thus reducing overall noise and spurs.
Solution Approach 2:
The integer path is activated periodically only during frequency acquisition and turned off during locked operation. This reduces the time high-speed transistors are active, thereby reducing the generation of noise and spurs while maintaining processing speed when needed.
4Reliability
If circuitry is kept active for continuous operation, then reliability improves, but power consumption increases
Solution Approach 1:
The integer path circuitry is activated periodically during frequency acquisition and then turned off during normal locked operation. The fractional TDC path remains active continuously to maintain locking, providing a balance between reliability and power consumption.
Solution Approach 2:
The lock detector automatically monitors PLL status and controls the gating of the integer path, enabling the system to self-manage power consumption based on operational state without external intervention, thus maintaining reliability while reducing power usage.
Data Source
AI summary
A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.