All-Digital PLL Lock-In Using Segmented Frequency Tuning
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Solution Overview
Problem
Traditional phase-locked loops experience long lock-in times, which are sensitive to frequency differences between oscillators' initial and final frequencies and loop bandwidth, making them inefficient in deep-submicron technology where analog circuits face challenges with noise immunity and jitter performance.
Innovation Solution
An all-digital phase-locked loop with a digitally controlled oscillator, utilizing LC-tank tuning circuits including MOM, coarse, and integer varactors, and a bang-bang phase detector to adjust frequencies and align clock edges, enabling/disabling tuning elements to minimize lock-in time and extend tracking range over voltage and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional phase-locked loop is used, then the system is simpler to implement, but the lock-in time is long and sensitive to frequency differences and loop bandwidth
Solution Approach 1:
The tuning range is divided into multiple segments with different tuning resolutions. The first tuning circuit provides coarse frequency adjustment with larger tuning steps, while the second tuning circuit provides fine frequency adjustment with smaller tuning steps. This segmentation allows the system to quickly acquire frequency lock while maintaining precision, significantly reducing lock-in time without requiring a single complex high-resolution tuning circuit across the entire frequency range.
Solution Approach 2:
The system dynamically switches between different tuning circuits and tuning resolutions based on the current frequency offset. When the frequency difference is large, the system uses the first tuning circuit with larger tuning steps for fast acquisition. When the frequency difference becomes small, the system switches to the second tuning circuit with finer resolution for precise locking. This dynamic adaptation optimizes the lock-in process at different stages.
2Adaptability or versatility
If the number of tuning circuit elements in the second tuning circuit is increased to extend tracking range, then the tracking range over voltage and temperature variations is extended, but the area cost increases
Solution Approach 1:
The tuning function is segmented between two tuning circuits with different characteristics. The first tuning circuit handles coarse frequency adjustment and provides part of the tracking range, while the second tuning circuit handles fine frequency adjustment and provides the remaining tracking range. This segmentation allows the system to achieve a wide total tracking range without requiring an excessive number of elements in a single high-resolution tuning circuit, thus reducing area cost.
Solution Approach 2:
Different parts of the tuning range are handled by different tuning circuits with optimized characteristics for their specific functions. The first tuning circuit is optimized for large frequency adjustments with larger tuning steps, while the second tuning circuit is optimized for small frequency adjustments with finer resolution. This local optimization allows each circuit to use fewer elements while collectively providing wide tracking range and fine precision.
3Reliability
If analog circuits are used in phase-locked loop, then the circuit can operate at lower supply voltages, but the jitter performance is degraded due to leakage currents
Solution Approach 1:
The patent replaces analog circuits with digital circuits throughout the phase-locked loop system. The voltage-controlled oscillator is converted to a digitally controlled oscillator, the analog loop filter is replaced with a digital loop filter, and the charge-pump phase-frequency detector is replaced with a digital timing-error detector. This digital substitution eliminates the jitter caused by analog leakage currents while maintaining compatibility with deep-submicron technology and low supply voltages.
4Loss of time
If the loop bandwidth is increased to reduce lock-in time, then the lock-in time is reduced, but the system becomes more sensitive to noise and jitter
Solution Approach 1:
The frequency acquisition process is segmented into two stages with different bandwidth characteristics. The first tuning circuit enables a wider effective bandwidth for fast initial frequency acquisition, while the second tuning circuit provides finer control for precise final locking. This segmentation allows the system to achieve fast lock-in time without requiring the entire system to operate at high bandwidth, thereby reducing noise and jitter sensitivity during the locking process.
Data Source
AI summary
An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.