Digital PLL Lock Detection Using Phase and Frequency Sampling
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Solution Overview
Problem
Conventional PLL lock detectors rely heavily on analog components, which are difficult to mass produce reliably and are less portable across different process technologies, making them less desirable for modern digital applications.
Innovation Solution
A digital lock detector is developed using digital components, specifically a frequency divider, counter, decoder, and phase sampler, to detect whether a PLL voltage-controlled oscillator (VCO) clock is locked to both the phase and frequency of a reference clock, outputting a LOCK signal to indicate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog components (low pass filter and comparator) are used to detect PLL lock condition, then the lock detection function can be achieved, but the manufacturing reliability and portability across process technologies deteriorate
Solution Approach 1:
The patent replaces the analog detection system (low pass filter and comparator) with a digital detection system using D-flip-flops and logic gates. Specifically, the analog integrator and comparator are substituted by digital components including first and second D-flip-flops, along with associated logic gates (AND, OR, NOT gates), thereby eliminating the manufacturing reliability issues inherent in analog designs while maintaining the lock detection function
Solution Approach 2:
The patent changes the detection parameters from analog voltage levels to digital phase and frequency relationships. The lock condition is detected by comparing digital phase samples and frequency counts rather than analog voltage levels, enabling the system to achieve reliable lock detection across different process technologies through parameter transformation from analog to digital domain
2Adaptability or versatility
If analog components are used in PLL lock detector, then lock detection is possible, but portability to various process technologies worsens
Solution Approach 1:
The patent substitutes analog components with digital components that are more portable across process technologies. The digital logic implementation using D-flip-flops and standard logic gates provides better adaptability to different CMOS process technologies compared to analog filters and comparators, while maintaining consistent manufacturing reliability across production batches
3Ease of manufacture
If digital components are used to detect PLL lock condition, then manufacturing reliability and portability are improved, but the device complexity increases
Solution Approach 1:
The patent segments the lock detection function into distinct digital modules: a phase detection module using D-flip-flops to compare phase samples, and a frequency detection module using counters to verify frequency matching. This segmentation allows each module to be independently optimized and manufactured, improving ease of mass production while organizing the complexity into manageable functional blocks
Solution Approach 2:
The digital components used in the patent, particularly the D-flip-flops and logic gates, serve multiple functions: they detect phase relationships, verify frequency locking, and generate the final lock indicator signal. This multi-functionality reduces the overall component count compared to a purely analog implementation and simplifies the manufacturing process across different process technologies
Data Source
AI summary
Circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit are provided. A frequency divider outputs a clock having a frequency equal to a reference clock frequency divided by N. A counter counts the number (M) of clock edges of a PLL output clock received during a given time interval of the frequency-divided reference clock. When M satisfies a predetermined relationship to N (e.g., M=N), the PLL output clock is locked to the frequency of the reference clock. A phase sampler compares the phases of the PLL output clock, a delayed PLL output clock and either the reference clock or a delayed reference clock. When the phase of the reference clock or delayed reference clock is between the phases of the PLL output clock and the delayed PLL output clock, the PLL output clock is also locked to the phase of the reference clock.