Digital PLL Phase/Frequency Detector for Shorter Lock Time
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Solution Overview
Problem
Conventional PLL designs face limitations in miniaturization, high costs, and long lock times due to large circuit dimensions and power consumption, especially in analog PLLs, and prior-art digital PLLs require complex circuitry for multi-mode operation, which increases parasite effects and limits operation speed.
Innovation Solution
A simple-structured digital PLL with a phase/frequency detector module that includes a counting clock input terminal, reference clock input terminal, phase error output terminal, frequency error output terminal, edge detector, counter, and frequency phase converter, which dynamically outputs frequency and phase errors to support multi-mode operation without the need for complex devices like TDCs and MMDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog PLL is used with low loop bandwidth frequency, then the resistance and capacitance become substantially large, but this makes it impossible to incorporate components into a single chip, increasing circuit dimensions and costs
Solution Approach 1:
The patent replaces the analog PLL system with a digital PLL system, substituting digital circuitry for analog components. This eliminates the need for large resistors and capacitors required in analog PLLs for low loop bandwidth operation, enabling single-chip integration while maintaining low loop bandwidth functionality.
2Speed
If analog PLL operates with low loop bandwidth frequency, then large dimension devices are required, but this results in leakage current and slower response speed, increasing lock time
Solution Approach 1:
The digital PLL architecture replaces analog circuitry that suffers from leakage current with digital logic circuits. This substitution eliminates the leakage current issue inherent in analog devices with large dimensions, enabling faster response speed and shorter lock time while operating at low loop bandwidth frequencies.
3Adaptability or versatility
If multi-mode design is implemented in analog PLL, then flexibility is improved, but the circuit complexity and design difficulty increase significantly
Solution Approach 1:
The digital PLL is designed with universal circuit blocks that can operate in multiple modes (phase-locked mode and frequency-locked mode) without requiring separate dedicated circuits for each mode. This multi-functionality approach enables flexible mode switching while maintaining relatively simple circuit architecture compared to traditional analog multi-mode designs.
4Measurement precision
If charge pump unit is used in analog PLL loop filter, then frequency control is improved, but mismatch due to process variation and temperature changes causes offset on output frequency or phase
Solution Approach 1:
The patent replaces the charge pump unit and analog loop filter with digital circuitry. This substitution eliminates the charge pump mismatch issue caused by process variation and temperature changes, as digital logic circuits are much less sensitive to these environmental factors, thereby improving output frequency and phase stability.
5Measurement precision
If prior-art digital PLL uses TDC circuit for time-to-digital conversion, then phase detection capability is improved, but the circuit area and power consumption increase
Solution Approach 1:
The patent extracts and removes the TDC (time-to-digital converter) circuit from the digital PLL architecture. Instead of using a separate TDC block for phase detection, the invention integrates phase detection functionality directly into the existing digital logic, significantly reducing circuit area and power consumption while maintaining phase detection capability.
6Adaptability or versatility
If prior-art digital PLL implements multi-mode operation with separate circuit blocks, then operational flexibility is improved, but parasite effects increase and operation speed is limited
Solution Approach 1:
The patent merges the functionality of separate circuit blocks (phase detector, frequency detector, and mode control) into a unified digital logic structure. This integration reduces the number of interconnections and interfaces between blocks, thereby minimizing parasite effects and enabling faster operation speed while maintaining multi-mode operational flexibility.
Data Source
AI summary
A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.