Digital PLL Lock Detection With Adjustable Locking Window

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Solution Overview

Problem

Existing lock detectors for phase-locked loops (PLL) are susceptible to errors due to variations in analog delay circuits caused by process, temperature, and bias voltage changes, making them unreliable for determining phase and frequency synchronization.

Innovation Solution

An adjustable digital lock detector using a variable counter, latch, lead/lag detector, and arbiter, which establishes a digitally-controlled locking window by adjusting a count number and offset values to determine lock conditions, reducing vulnerability to environmental variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If analog delay circuits are used in the lock detector, then the locking window can be established, but the delays are susceptible to process, temperature, and bias voltage variation

Engineering Contradiction:

Improvelock detection reliabilityVSAvoidsensitivity to process, temperature, and bias voltage variation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces analog delay circuits with a digital implementation using a counter and programmable delay mechanism. The delay is achieved by counting clock cycles rather than using analog timing circuits, thereby substituting a digital system for an analog one. This resolves the technical contradiction by eliminating the sensitivity to process, temperature, and bias voltage variations inherent in analog delay circuits while maintaining the locking window functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces programmable parameters (counter values and clock frequencies) to define the locking window characteristics. By changing digital parameters rather than relying on fixed analog delay characteristics, the system achieves stability against environmental variations. The delay period is determined by digital counts of clock cycles, making it immune to the physical variations that affect analog circuits.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If a fixed locking window is used in the lock detector, then the phase comparison can be performed, but the locking window cannot be adjusted for different applications

Engineering Contradiction:

Improvelocking window adjustabilityVSAvoidadaptability to different phase error tolerances

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic locking window by allowing programmable adjustment of the counter values that define the window boundaries. Instead of a fixed analog delay, the digital counter can be reconfigured through software or control signals to change the locking window width and position. This enables the system to adapt to different phase error tolerances and application requirements while maintaining ease of operation through programmable control.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7595672B2Adjustable digital lock detector

Publication Date: 2009.09.29 RICHWAVE TECH CORP

AI summary

An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.