All-Digital PLL Loop Filter Without Signal Synthesis Blocks
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Solution Overview
Problem
Conventional digital phase-locked loops are complex and time-consuming to verify due to the incorporation of signal synthesis blocks and circuits, increasing complexity and calculation time.
Innovation Solution
An all-digital phase-locked loop design that employs a digital loop filter comprising a selection circuit, operation circuits, register circuits, and time-to-digital conversion circuits to output control signals for a digitally controlled oscillator, eliminating the need for signal synthesis blocks and simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital loop filter is implemented using a signal synthesis block for digital coding, an integrator and an adder, then the phase-locked loop can process phase difference signals, but the complexity and calculation time increase during verification
Solution Approach 1:
The patent extracts and removes the signal synthesis block for digital coding from the digital loop filter implementation. By eliminating this complex component while retaining the essential functionality of the integrator and adder circuits, the verification complexity is reduced without sacrificing phase difference processing capability
Solution Approach 2:
The patent uses a simplified digital circuit model that copies only the essential operational characteristics of the phase-locked loop system. This abstracted model enables verification of the core functionality without the computational burden of implementing all signal synthesis details
2Reliability
If a digital loop filter is implemented using a signal synthesis block for digital coding, an integrator and an adder, then the phase-locked loop can process phase difference signals, but the calculation time increases during verification
Solution Approach 1:
By extracting and removing the computationally intensive signal synthesis block from the verification model, the patent significantly reduces calculation time while preserving the essential phase difference processing functionality through the simplified integrator and adder implementation
3Ease of manufacture
If conventional digital loop filter circuits are used, then the phase-locked loop can be implemented with standard components, but the verification process becomes complex and time-consuming
Solution Approach 1:
The patent creates a simplified digital circuit model that copies only the essential operational characteristics of the phase-locked loop system. This abstracted verification model maintains implementation feasibility while dramatically reducing verification complexity compared to conventional detailed circuit models
Data Source
AI summary
The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.