Digital PLL Dynamic Loop Gain for Jitter and Response Balance
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Solution Overview
Problem
Digital phase-locked loops (PLLs) face challenges with quantization noise and power-supply-induced jitter due to the tradeoff between dithering jitter and reaction speed, particularly in digitally controlled oscillators (DCOs), where smaller step sizes reduce dithering but increase system slowness in responding to power supply changes.
Innovation Solution
A digital PLL design with a bang-bang phase detector and a loop-parameter control unit (LPCU) dynamically adjusts loop-filter parameters based on observed patterns of up/down values from the phase detector output, increasing DCO step size during disturbances and decreasing it when the condition ends, to balance jitter reduction and reaction speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the DCO step size is made smaller, then dithering jitter is reduced, but the system becomes slower to react to power supply changes
Solution Approach 1:
The patent implements dynamic loop gain control that adjusts the DCO step size based on operating conditions. The loop gain is increased when power supply changes are detected (improving reaction speed) and decreased during steady-state operation (reducing dithering jitter). This dynamic adjustment resolves the contradiction by making the step size adaptive rather than fixed.
Solution Approach 2:
The patent changes the DCO step size parameter dynamically based on the detected power supply conditions. By modifying this key parameter in response to environmental changes, the system optimizes performance across different operating states, achieving both low jitter and fast response when needed.
2Speed
If the DCO step size is made larger, then the system reacts faster to power supply changes, but dithering jitter increases
Solution Approach 1:
The loop gain control mechanism dynamically adjusts the DCO step size based on real-time detection of power supply stability. During transient conditions, the gain is increased for faster response; during steady-state, the gain is reduced to minimize jitter. This dynamic behavior resolves the contradiction.
Solution Approach 2:
The system modifies the DCO step size parameter in response to detected conditions, using parameter changes to optimize the trade-off between response speed and jitter generation across different operating states.
Data Source
AI summary
The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector.