Variable-Gain Digital PLL for Faster Low-Frequency Locking
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Solution Overview
Problem
Conventional digital phase-locked loops take an excessively long time to lock for low-frequency input clock signals, such as those used in GPS or distributed timing applications, which degrades performance and fails to meet target locking times of less than one minute, especially when the input clock signal is lost and recovered.
Innovation Solution
A digital phase-locked loop method that updates the gain of a variable gain digital filter using an estimate error of the current phase and frequency of the input clock signal, along with measurement errors, incorporating a proportional and integral gain component, to quickly converge and lock to the target signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional digital phase-locked loop with a fixed gain PI controller is used, then the system is simple and stable, but the lock time becomes excessively long for low-frequency input clock signals
Solution Approach 1:
The patent implements a variable gain digital filter where the gain is dynamically adjusted based on the current locking state. The controller transitions between different gain values (e.g., first gain value during acquisition, second gain value during tracking) to optimize both lock time and stability. This dynamic adaptation allows the system to achieve fast locking for low-frequency signals while maintaining stability during normal operation.
Solution Approach 2:
The patent changes the gain parameter of the digital filter based on the estimated locking state. By monitoring parameters such as phase error and frequency error, the system adjusts the gain parameter to achieve optimal performance at different stages of the locking process, thereby reducing overall lock time without sacrificing stability.
2Loss of time
If the loop bandwidth is increased to reduce lock time, then the locking speed improves, but the measurement precision and stability of the phase and frequency estimation deteriorate
Solution Approach 1:
The patent dynamically adjusts the loop bandwidth by changing the gain of the digital filter based on the locking state. During the acquisition phase, a wider bandwidth (higher gain) is used to achieve fast locking. Once locked, the system transitions to a narrower bandwidth (lower gain) to improve measurement precision and reduce noise, thereby resolving the trade-off between lock time and estimation precision.
Solution Approach 2:
The system periodically evaluates the locking state and adjusts the gain accordingly, creating a periodic action pattern where the loop bandwidth is expanded during acquisition and contracted during tracking. This periodic adjustment allows the system to achieve both fast locking and high precision measurements at different appropriate times.
Data Source
AI summary
A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.