Digital PLL Current-Source Switching for Low Jitter Lock
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Solution Overview
Problem
Conventional digital phase locked loops (DPLLs) experience high frequency jitter due to current surges generated by switching of DAC current sources, leading to increased switching noise.
Innovation Solution
Implementing a DPLL with binary and thermometric current control, where binary current control word bits control switching before frequency lock and thermometric control word bits control after lock, reducing current surges by stabilizing the second set of current sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If binary weighted current sources are used in the DAC for frequency control, then the DPLL can achieve frequency lock, but large current surges are generated during switching leading to high frequency jitter
Solution Approach 1:
The current sources are divided into two separate sets: first current sources for frequency control and second current sources for phase control. This segmentation allows each set to be optimized for its specific function, with the second set using thermometric coding to minimize switching noise during phase adjustments after frequency lock is achieved.
Solution Approach 2:
A dual control word mechanism is introduced where the first control word manages frequency control and the second control word manages phase control. This intermediary control structure prevents direct switching of all current sources during phase adjustments, thereby reducing current surges and high frequency jitter.
2Stability of the object's composition
If conventional binary weighted current sources are switched to maintain frequency lock, then frequency stability is achieved, but switching noise increases due to instantaneous current magnitude changes
Solution Approach 1:
Different coding schemes are applied to different portions of the current control function. Binary weighted coding is used for frequency control where large steps are needed, while thermometric coding is used for phase control where fine adjustments with minimal switching noise are required. This local differentiation of control quality optimizes both frequency stability and noise reduction.
Solution Approach 2:
The patent changes the control parameter representation from a single binary control word to two separate control words with different coding schemes. The first control word uses binary weighting for frequency steps, while the second control word uses thermometric coding for phase adjustments, thereby changing how current sources are controlled to reduce switching noise.
Data Source
AI summary
A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.