Reconfigurable Digital PLL Architecture for Low-Spur Multi-Standard RF
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Solution Overview
Problem
Conventional all digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unacceptable RF spurs due to their hardwired design.
Innovation Solution
A software-based phase locked loop architecture using a reconfigurable calculation unit (RCU) and application-specific instruction-set processor (ASIP) that allows for programmable operation, reducing silicon area and current transients by performing all computations within one reference clock cycle and shifting the frequency of switching logic gates to higher processor clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a hardwired circuit design is used for ADPLL, then the circuit operates at lower speed with dedicated hardware, but it provides fixed functionality with limited reconfigurability
Solution Approach 1:
The patent applies dynamics by transitioning from a static hardwired circuit to a dynamic reconfigurable architecture. The ADPLL uses a microprocessor that can be reprogrammed via software to change its functionality, allowing the same hardware to adapt to different wireless standards and applications. This enables the circuit to dynamically adjust its operation mode, filter characteristics, and frequency synthesis parameters without physical reconfiguration.
Solution Approach 2:
The patent implements parameter changes by using software-controlled registers and configuration bits that allow modification of operational parameters such as loop bandwidth, division ratios, and filter coefficients. The microprocessor can load different parameter sets from memory to switch between GSM, WCDMA, Bluetooth, and other standards, providing versatility while maintaining high-speed operation.
2Reliability
If a hardwired circuit design is used for ADPLL, then the design is committed to physical implementation, but any modification requires numerous time consuming steps in the ASIC creation process
Solution Approach 1:
The patent applies copying by storing multiple ADPLL configuration sets and parameter tables in on-chip memory or external memory. Instead of creating multiple physical ASIC versions, the system copies the desired configuration from memory to the microprocessor registers, enabling rapid switching between different standards and applications without going through the lengthy ASIC re-spining process.
Solution Approach 2:
The patent implements universality by designing a single microprocessor-based ADPLL core that can perform multiple functions across different wireless standards. The universal architecture includes programmable dividers, configurable loop filters, and flexible frequency synthesis logic that can be programmed to support GSM, WCDMA, Bluetooth, WiFi, and other standards, eliminating the need for separate dedicated circuits for each application.
3Ease of manufacture
If conventional ADPLL circuits are used, then they provide fixed hardware implementation, but they generate significant current transients that result in unacceptable RF spurs
Solution Approach 1:
The patent applies periodic action by using pulse-density modulation (PDM) and sigma-delta modulation techniques to spread the current transient energy over a wider frequency spectrum. Instead of concentrated current switches at the reference clock frequency, the modulator distributes the switching activity periodically at ultrasonic frequencies, pushing the spurious content away from the RF bands of interest and reducing in-band spurs.
Solution Approach 2:
The patent replaces the traditional charge-pump current switching mechanism with a digital pulse-density modulation approach. Instead of directly switching large currents at the reference clock frequency, the system uses a modulator to convert the frequency control word into a stream of pulses with varying density, thereby substituting the direct current switching mechanism with a softer, more spectrally efficient approach that reduces RF spur generation.
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.