Reconfigurable Digital PLL Parallelization for Lower RF Spurs
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Solution Overview
Problem
Conventional all-digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate unacceptable RF spurs due to current transients, which are challenging to filter out.
Innovation Solution
A software-based phase locked loop architecture with a reconfigurable calculation unit (RCU) that can perform all atomic operations of a phase locked loop, allowing for on-the-fly reconfiguration and reducing current transients by oversampling and spreading computations across higher processor clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardwired circuit design is used for ADPLL, then the circuit operates at lower speed with dedicated hardware, but the design lacks reconfigurability and cannot support multi-standard wireless applications
Solution Approach 1:
The patent implements a reconfigurable ADPLL architecture where the loop filter coefficients and other parameters can be dynamically changed through software control. This allows the same hardware circuit to be reconfigured for different wireless standards (GSM, WCDMA, LTE, etc.) without physical redesign, resolving the contradiction between adaptability and design complexity by making the system dynamically adjustable rather than statically fixed
Solution Approach 2:
The invention changes the approach from redesigning circuit topology to changing operational parameters. By allowing software-configurable parameters such as loop filter coefficients, charge pump current, and divider ratios, the system achieves multi-standard support through parameter modification rather than structural redesign, thus maintaining simplicity while improving adaptability
2Object-affected harmful factors
If conventional ADPLL computations are performed at the reference clock frequency, then the circuit is simple, but it generates unacceptable RF spurs due to current transients that are difficult to filter
Solution Approach 1:
The patent introduces oversampling by performing computations at a frequency that is an integer multiple (N times) of the reference clock frequency. This periodic action at a higher frequency spreads the current transient energy across multiple cycles, reducing the amplitude of spurs at the reference clock frequency and making them easier to filter, thus resolving the contradiction between reducing harmful RF spurs and maintaining computation speed
3Adaptability or versatility
If a software-based architecture with reconfigurable calculation unit is used, then multi-standard support and reduced RF spurs are achieved, but the device complexity increases due to additional control logic and memory structures
Solution Approach 1:
The patent employs a universal reconfigurable calculation unit that can perform multiple functions depending on the configured parameters. This single unit replaces what would otherwise require multiple dedicated hardware circuits for different standards, achieving multi-functionality that reduces overall system complexity while maintaining high adaptability across different wireless standards
Solution Approach 2:
The invention introduces a software layer as an intermediary between the control logic and the calculation unit. This software layer handles the complexity of reconfiguration and parameter management, allowing the hardware architecture to remain relatively simple while still achieving multi-standard support through software-controlled parameter adjustment
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.