Digital PLL Frequency Tuning During Mask Time for ULP RF

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Solution Overview

Problem

In ultra-low power (ULP) RF transceivers, the voltage-controlled oscillator (VCO) and phase-locked loop (PLL) consume excessive power, leading to high energy consumption and reduced accuracy due to continuous power application and lack of efficient frequency tuning mechanisms.

Innovation Solution

A digital phase-locked loop (DPLL) system that includes a counter to measure VCO information during a mask time, a comparator to compare this information with target frequency data, and a frequency tuner to adjust the oscillator frequency to a target frequency, minimizing power consumption by turning off unnecessary blocks and maintaining frequency accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous power is applied to the PLL and VCO in most RF transceivers, then frequency stability is maintained, but power consumption increases significantly

Engineering Contradiction:
Improvefrequency stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic frequency tuning by measuring VCO frequency at specific intervals (mask times) rather than continuously. The counter measures VCO information during mask times, and the frequency tuner adjusts frequency periodically based on these measurements, replacing continuous power application with periodic action to reduce power consumption while maintaining frequency stability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses the existing mask times (which occur naturally during data transmission/reception cycles) to perform frequency measurements and tuning. By utilizing these pre-existing time intervals for self-diagnosis and self-adjustment, the system maintains frequency stability without requiring dedicated continuous power to the PLL and VCO, thereby reducing overall power consumption.

Inventive Principle:
Principle #25Self-service

2Use of energy by moving object

If a digital phase-locked loop (DPLL) measures VCO information during mask times and tunes frequency periodically, then power consumption is reduced, but frequency tuning accuracy may be affected

Engineering Contradiction:
Improvepower consumptionVSAvoidfrequency tuning accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the counter measures actual VCO frequency during mask times, compares it with the target frequency, and the frequency tuner adjusts the VCO frequency based on this feedback. This closed-loop feedback system ensures that periodic measurements and adjustments maintain frequency tuning accuracy while reducing power consumption compared to continuous operation.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs frequency measurements and adjustments during mask times, which are pre-existing intervals in the communication protocol. By utilizing these predetermined time windows for frequency calibration before data transmission/reception, the system ensures frequency accuracy is maintained without requiring continuous power consumption.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If high-power components are eliminated to reduce power consumption, then energy efficiency improves, but device complexity may increase

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent replaces the traditional analog PLL mechanism with a digital implementation. The counter measures VCO frequency by counting oscillations during mask times, and the frequency tuner uses digital control to adjust the VCO. This digital substitution eliminates the need for continuous power application to analog PLL components while managing device complexity through integrated digital logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The counter and frequency tuner components serve multiple functions: they measure VCO frequency, compare it with target frequency, determine frequency errors, and generate adjustment signals. By making these components multi-functional, the patent reduces the need for separate dedicated components, thereby managing device complexity while achieving power consumption reduction through periodic operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9413369B2Digital phase-locked loop (DPLL), method of controlling DPLL, and ultra low power (ULP) transceiver using DPLL
Publication Date: 2016.08.09 SAMSUNG ELECTRONICS CO LTD
  • US9413369B2 patent drawing
  • US9413369B2 patent drawing
  • US9413369B2 patent drawing

AI summary

A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.