Digital PLL Mode Switching for Low-Power Phase Locking
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Solution Overview
Problem
Digital phase locked loop (D-PLL) circuits consume high power due to the continuous operation of the multi-modulus divider and retiming circuit at high frequencies, which affects their efficiency and energy usage.
Innovation Solution
The D-PLL circuit is designed to switch between a sampling mode and a subsampling mode, where in the subsampling mode, the divider is stopped, and phase locking is maintained using a delayed reference clock, reducing power consumption. Additionally, a mode selector and dead zone detector are implemented to prevent phase lock loss and false locking, and a duty cycled frequency lock loop is used to intermittently operate, further reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the multi-modulus divider and retiming circuit operate continuously at high frequency to maintain phase lock accuracy, then phase locking reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements a duty-cycled frequency lock loop that intermittently operates the phase locked loop circuit. The FLL detector operates periodically rather than continuously, checking frequency lock status at intervals. This periodic operation maintains phase locking reliability when needed while significantly reducing average power consumption during stable operation.
Solution Approach 2:
The patent dynamically switches between different operational modes based on lock status. When frequency lock is detected, the system transitions to a low-power mode where the phase locked loop is disabled. When lock is lost or initially acquiring, the system activates the full-phase locked loop operation. This dynamic adaptation resolves the contradiction by adjusting operation level to actual needs.
2Stability of the object's composition
If the phase locked loop operates continuously to maintain frequency multiplication, then output clock stability is improved, but energy efficiency deteriorates
Solution Approach 1:
The duty-cycled FLL detector performs periodic frequency lock detection rather than continuous monitoring. It checks whether the output clock frequency matches the expected multiplied frequency at intervals, maintaining stability verification while reducing energy consumption associated with continuous operation of the entire phase locked loop system.
Solution Approach 2:
The FLL detector provides feedback about frequency lock status to control the operation of the phase locked loop. When feedback indicates stable frequency multiplication, the system reduces operation to maintain energy efficiency. When feedback indicates frequency drift or loss of lock, the system activates full operation to restore stability.
3Measurement precision
If the divider operates at high frequency to maintain accurate phase feedback, then phase detection accuracy is improved, but power consumption increases
Solution Approach 1:
The phase detection and feedback operation is performed periodically rather than continuously. The FLL detector checks frequency and phase relationships at intervals, maintaining sufficient detection accuracy for lock determination while allowing the divider and retiming circuit to operate at reduced power during stable locked conditions.
Solution Approach 2:
The system performs full-phase detection and feedback operation only when necessary (during acquisition or when lock is suspected to be lost). During stable operation, reduced monitoring is sufficient to maintain lock, allowing partial operation that consumes less energy while maintaining adequate phase detection accuracy for the locked state.
Data Source
AI summary
With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.