Digital Phase-Locked Loop Without Re-Sampling Noise
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Solution Overview
Problem
Conventional analog phase locked loops (PLLs) face limitations due to noise from analog elements and difficulties in achieving high bandwidth and low noise performance, whereas digital PLLs offer improved stability and flexibility but are susceptible to noise during the re-sampling process.
Innovation Solution
A digital phase locked loop design that eliminates physical feedback transitions by operating entirely in the digital domain, using a phase acquisition unit, digital phase detector, digital loop filter, and digital controlled oscillator, allowing for simpler design and reduced noise through mathematical operations without domain transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional analog PLL is used, then the design is straightforward with physical feedback signals, but noise from analog elements (phase detector, charge pump) degrades performance and limits bandwidth
Solution Approach 1:
The patent replaces the analog mechanical system with a digital system. Specifically, analog signals are converted to digital domain through sampling, and the phase detector, loop filter, and controlled oscillator are all implemented as digital circuits. This substitution eliminates analog noise sources while maintaining PLL functionality through digital signal processing and mathematical operations.
Solution Approach 2:
The patent changes the operational parameters from analog continuous signals to digital discrete signals. By sampling the phase signal and representing it as digital values, the system can operate at extremely high bandwidths (up to 10 MHz) without the noise limitations of analog components. The parameter change from voltage/current domain to digital domain fundamentally alters the noise characteristics.
2Speed
If a digital PLL with re-sampling is used, then bandwidth can be increased to 10 MHz, but noise is added during the re-sampling process
Solution Approach 1:
The patent performs phase detection and filtering operations before the final digital controlled oscillator adjustment. By acquiring phase information in advance and processing it through digital filtering, the system prepares clean phase data that minimizes noise introduction during subsequent operations. This preliminary digital processing avoids the need for noisy re-sampling of analog feedback signals.
3Ease of operation
If analog elements are used in PLL, then physical feedback signals provide direct control, but noise is folded back into a small frequency band degrading performance
Solution Approach 1:
The patent replaces the analog feedback mechanism with a digital feedback loop. Instead of using physical analog feedback signals that subject noise folding, the system uses digital representations of phase information. The digital controlled oscillator responds to digital control words rather than analog voltages, eliminating the noise folding problem inherent in analog implementations while maintaining feedback control functionality.
Data Source
AI summary
A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.