Digital PLL Phase Noise Reduction via Parity Error Estimation
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Solution Overview
Problem
Digital Phase Locked Loops (DPLLs) face issues with aliasing and out-of-band noise conversion, leading to incorrect frequency corrections and limiting phase noise performance due to the digital domain conversion of phase measurements.
Innovation Solution
A circuit comprising an error signal estimator and a combiner that reduces noise by determining parity information and estimated error amplitudes, allowing for the mitigation of aliased spurs in the digital domain, and includes a reference clock generator to manage sampling rates and cycle parity, effectively reducing jitter and spur noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If phase measurement is converted to digital domain using TDC, then power consumption and area are reduced, but aliasing occurs causing out-of-band noise to be interpreted as in-band noise
Solution Approach 1:
An analog anti-aliasing filter is introduced as an intermediary component between the TDC and the digital processing stages. This filter selectively attenuates out-of-band noise components before they undergo digital conversion, preventing them from being misinterpreted as in-band signals. The filter acts as a mediator that preserves the digital domain's power efficiency while eliminating the aliasing problem that degrades measurement precision.
2Device complexity
If digital domain processing is used, then device complexity is reduced, but in-band spurs are generated due to incorrect frequency corrections
Solution Approach 1:
The anti-aliasing filter performs preliminary action by removing out-of-band noise components before they enter the digital domain. By pre-filtering the analog phase measurement signal, the system prevents the generation of incorrect frequency corrections that would otherwise create in-band spurs. This preliminary filtering action maintains the simplicity of digital processing while eliminating the harmful spurious signals.
3Measurement precision
If anti-aliasing filter is added to reduce noise, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The anti-aliasing filter is designed with specific parameter optimizations including selective frequency response characteristics and quality factor (Q) values that are tailored to the DPLL operating conditions. By carefully selecting the filter's bandwidth and cutoff frequency parameters, the design achieves effective noise reduction while minimizing the filter's order and component count, thus limiting the increase in device complexity.
Data Source
AI summary
A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.