All-Digital PLL Phase Coherence Across Multi-Channel Frequency Switching
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Solution Overview
Problem
Existing narrow-band radios face ambiguity in channel phase state information due to multipath in non-line of sight channels, leading to inaccuracies in ranging measurements, especially when channels are concatenated.
Innovation Solution
An all-digital phase locked loop (ADPLL) with a pattern generator, phase accumulator, phase comparator, and control means, utilizing a two-point modulation scheme and capacitor banks to maintain phase coherence across frequency changes, allowing predictable phase relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If narrow-band radios concatenate multiple channels to achieve virtual-wideband ranging, then ranging accuracy is improved, but phase ambiguity occurs due to multipath in non-line of sight channels
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing phase compensation values in a lookup table before ranging operations. The phase compensation values are computed based on expected phase deviations across multiple channels, allowing the system to quickly retrieve and apply corrections without real-time computation, thus resolving phase ambiguity while maintaining high ranging accuracy
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase state information across concatenated channels and using a phase unwrapping algorithm to detect and correct phase ambiguities. The system compares measured phase differences with expected values and applies corrective transformations to eliminate multipath-induced phase errors, thereby maintaining accurate ranging measurements
2Measurement precision
If phase coherent measurements are maintained over multiple channels, then the number of unknown parameters is reduced, but the complexity of maintaining phase coherence increases
Solution Approach 1:
The patent applies segmentation by dividing the phase coherence maintenance task into independent per-channel measurements. Each channel's phase state is measured and processed separately using identical algorithms, allowing parallel processing and reducing overall system complexity. The segmentation enables modular implementation where the same phase unwrapping logic can be applied independently to each channel's data
Solution Approach 2:
The patent uses parameter changes by transforming the phase measurements from raw phase values to unwrapped phase values through a systematic parameter transformation. The phase unwrapping algorithm changes the parameter representation from ambiguous modulo-2π values to continuous phase values, reducing the number of unknown parameters while maintaining measurement accuracy across all channels
3Adaptability or versatility
If digital phase-locked loops switch frequencies during channel switching, then multi-carrier ranging is enabled, but predictable phase relationships are lost
Solution Approach 1:
The patent applies preliminary action by pre-calculating phase trajectory compensation values for each frequency transition in the multi-carrier system. Before switching between carriers, the system retrieves pre-computed phase correction values that account for the specific frequency change, ensuring that predictable phase relationships are maintained across all carrier transitions without requiring complex real-time phase tracking
Solution Approach 2:
The patent uses copying by replicating the phase trajectory compensation approach across multiple carriers. The same phase unwrapping algorithm and compensation methodology are copied and applied to each carrier's phase measurements, ensuring consistent and predictable phase relationships throughout the multi-carrier ranging process. This copying approach simplifies the system by using identical processing logic for all frequency transitions
Data Source
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Figure 3A~3B
AI summary
An all-digital phase locked loop (ADPLL) (10) is provided. The ADPLL (10) comprises a pattern generator (11) adapted to generate a frequency control word (FCW) (14) based on a predefined setting (12) and a system clock (13). In addition, the ADPLL (10) comprises a phase accumulator (15) adapted to translate the FCW (14) into a phase trajectory (16). The ADPLL (10) further comprises a phase comparator (17) adapted to generate a phase error signal (18) representing a difference between the phase trajectory (16) and the phase of an output oscillation frequency (25). Moreover, the ADPLL (10) comprises a control means (20) adapted to control a phase of the output oscillation frequency (25) with respect to the phase trajectory (16).