Digital PLL Reconfiguration for Stable Frequency and Phase Control
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Solution Overview
Problem
Existing phase-locked loops (PLLs) are not reconfigurable, making them difficult to use with configurable circuitry like FPGAs and requiring fixed IC layouts, which limits their flexibility in frequency range, jitter level, power usage, and temperature variations.
Innovation Solution
A reconfigurable, digital phase-locked loop that generates a frequency reference or delay with phase detection, allowing configuration for various parameters such as frequency, bandwidth, jitter level, and power consumption, and can be integrated into any IC design with a variable layout, using a circuitry netlist and standard cells of any silicon fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed IC layout PLL design is used, then manufacturing simplicity is improved, but adaptability to different IC designs deteriorates
Solution Approach 1:
The PLL design transitions from a fixed, static layout to a dynamic, reconfigurable architecture where circuit blocks can be selectively enabled or disabled based on configuration parameters. This allows the same physical layout to adapt to different design requirements while maintaining manufacturing simplicity.
Solution Approach 2:
The PLL circuit is designed with universal, multi-functional blocks that can serve different purposes based on configuration. The same oscillator, divider, and phase detector circuits can operate in multiple modes, allowing a single design to replace multiple specialized designs.
2Device complexity
If a non-reconfigurable PLL is used, then circuit simplicity is improved, but configurability for frequency range and power usage deteriorates
Solution Approach 1:
The PLL is divided into independent, modular functional blocks (oscillator, divider, phase detector, loop filter) that can be independently configured and optimized. This segmentation allows each block to be tuned for specific frequency ranges or power consumption levels without redesigning the entire circuit.
Solution Approach 2:
The PLL incorporates configurable parameters such as division ratios, oscillator frequencies, and loop filter values that can be adjusted to optimize performance for different frequency ranges and power consumption requirements, maintaining circuit simplicity while enhancing adaptability.
3Stability of the object's composition
If a fixed frequency PLL is used, then circuit stability is improved, but frequency resolution and adaptability deteriorate
Solution Approach 1:
The PLL uses feedback mechanisms where the phase detector continuously monitors the output frequency and adjusts the control voltage to maintain accurate frequency synthesis. This feedback ensures circuit stability while enabling fine frequency resolution through digital control of division ratios and oscillator frequencies.
Data Source
AI summary
A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.