Digital PLL Loop Filter Switching for Faster Phase Convergence
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Solution Overview
Problem
Digital phase locked loops (DPLLs) with low loop bandwidth experience excessively long convergence times when frequency is in lock with a small frequency offset, as the phase error convergence relies on the integral part, leading to slow phase lock, which is unacceptable for data transmission applications.
Innovation Solution
A control module activates a switch to temporarily replace the integral component of the loop filter with the control signal in the delayed feedback loop when the phase error is non-zero and the rate of phase change is below a threshold, allowing the proportional part to govern convergence without altering the DPLL behavior or bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the loop bandwidth is reduced to reduce jitter, then the jitter is reduced, but the convergence time becomes excessively long
Solution Approach 1:
The patent dynamically switches the loop filter configuration between two modes: normally operating in second-order mode for jitter reduction, and temporarily switching to first-order mode when phase error convergence slows down. This dynamic adaptation allows the system to maintain low jitter during normal operation while accelerating convergence when needed, resolving the contradiction between jitter reduction and convergence time.
2Measurement precision
If the integral part accumulates phase errors to maintain frequency offset, then frequency accuracy is improved, but the residual phase convergence becomes extremely slow
Solution Approach 1:
The patent implements periodic monitoring of the phase error convergence rate and periodically switches the loop filter order when convergence slows down. The control module detects when the phase error change falls below a threshold and temporarily activates the first-order mode, creating a periodic control action that maintains frequency accuracy while preventing excessively slow convergence.
3Loss of time
If the scaling factor I is increased to speed up phase convergence, then convergence time is reduced, but the frequency response and bandwidth behavior are impacted
Solution Approach 1:
The patent segments the convergence process into two phases: initial convergence handled by the proportional part with fast response, and residual convergence that may require integral accumulation. By temporarily switching to first-order mode when residual convergence slows down, the system accelerates the second phase without permanently altering the integral component's role in maintaining frequency accuracy, thus avoiding impact on overall frequency response behavior.
Data Source
AI summary
A digital phase locked loop has a digital controlled oscillator, a phase comparator comparing the output signal of the digital controlled oscillator, or a signal derived therefrom, with a reference signal to produce a phase error signal. A loop filter produces a control signal for the digital controlled oscillator from an output of the phase comparator the loop filter. The loop filter has a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder receiving the respective proportional and integral components at first and second inputs thereof to produce the control signal. The integral part includes a delayed feedback loop normally configured to accept the integral component at an input thereof. A first switch replaces the integral component at the input of the delayed feedback loop by the control signal in response to an activation signal. A control module produces the activation signal to activate the switch for brief periods when the phase error is non-zero and the rate of change of phase is less than a threshold value.