Digital PLL Clock Generation With Oversampled Phase Detection
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Solution Overview
Problem
Digital phase-locked loops (PLLs) face challenges in accurately determining phase deviations between reference and local clocks, leading to potential scanning errors and disruptions in digital data streams, as existing methods may not provide continuous information about phase shifts.
Innovation Solution
A system clock independent of the reference and local clocks is used, with a frequency at least five times higher, allowing for 'oversampling' by setting the time interval between clock edges greater than the sampling pulses, ensuring accurate phase detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital phase detector with a common clock is used to regulate clock frequency, then the circuit structure is simplified, but scanning errors occur due to insufficient phase detection information
Solution Approach 1:
The patent segments the clock signal path by introducing a separate system clock independent of the reference and local clocks. This segmentation allows the phase detector to operate with a higher frequency system clock while maintaining accurate phase detection of the lower frequency reference and local clocks, thereby resolving the contradiction between simplified digital circuitry and reliable phase detection.
Solution Approach 2:
The patent changes the frequency parameter of the sampling clock by introducing a system clock with frequency at least five times higher than the reference or local clock. This parameter change enables oversampling in the phase detector, providing sufficient phase detection information without increasing the complexity of the overall circuit structure.
2Measurement precision
If the common clock frequency is increased to improve sampling accuracy, then phase detection precision improves, but the risk of faulty sampling increases due to timing conflicts
Solution Approach 1:
The patent applies preliminary action by setting the time interval between clock edges greater than the sampling pulse interval before any phase detection occurs. This preliminary timing arrangement ensures that the higher frequency system clock samples phase information without missing critical edges, preventing faulty sampling while maintaining high detection precision.
Solution Approach 2:
The patent implements feedback through the phase-locked loop mechanism where the phase detector continuously compares the reference clock and local clock using the high-frequency system clock. The resulting phase error information is fed back to adjust the local clock frequency, ensuring that high sampling precision translates into accurate frequency regulation without faulty sampling.
3Measurement precision
If a multiplexer with delay circuit is added to scan phase positions, then phase alignment accuracy improves, but the device complexity increases
Solution Approach 1:
The patent applies universality by using the high-frequency system clock to serve multiple functions: it acts as the sampling clock for the phase detector, provides timing control for the multiplexer, and ensures proper synchronization throughout the circuit. This multi-functionality achieves accurate phase alignment without adding excessive complexity, as the system clock replaces the need for multiple specialized clock sources.
Data Source
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AI summary
The invention relates to a method for generating a clock frequency as a function of a reference clock pulse (RT), wherein an arrangement is utilized comprising a digital phase detector (PD), a loop filter (LF) connected to the same, and a digital/analog converter (DU) connected to the same, all of which are charged with a common clock pulse (ST). A crystal-stable, controllable oscillator (VCO) is connected to the output of the digital/analog converter, said oscillator generating a local clock pulse (LT) that corresponds to the clock frequency as the output signal. The phase detector is supplied with the reference clock pulse as the first input signal via a first input, and with the local clock pulse as a second input signal via a second input. A multiplexer is interconnected from one of the inputs of the phase detector into the transmission path of the respective incoming input signal, said multiplexer being provided with the corresponding input signal directly on one hand and in a delayed manner on the other hand. A system clock pulse that is independent of the reference clock pulse and the local clock pulse is utilized as a common clock pulse, the frequency of said system clock pulse being higher than the frequency of the reference clock pulse, or of the local clock pulse, by a factor of at least 5. The chronological distance between the edges of the non-delayed clock pulse, on the other hand, and the delayed clock pulse, on the other hand, is adjusted to be greater than the chronological distance of the adjustment pulses of the phase detector, which are specified by the system clock pulse.