Digital PLL Phase Estimation for TDC Quantization Noise
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face limitations due to quantization errors introduced by analog-to-digital converters, which affect phase noise performance and are not effectively mitigated without increasing power consumption or complicating circuit designs.
Innovation Solution
The implementation of an all-digital phase-locked loop (ADPLL) with an a-priori probability phase estimation (APPPE) component that utilizes statistical distributions and a-priori knowledge of the time-to-digital converter (TDC) to refine phase measurements and reduce quantization errors, allowing for improved phase noise performance without altering analog circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If quantization error mitigation techniques are applied to improve phase noise performance, then phase noise performance is improved, but power consumption increases
Solution Approach 1:
The patent implements a feedback mechanism where the estimated quantization error is fed back into the control loop to correct phase measurements. The estimator component continuously monitors quantized phase values and generates error corrections that are applied in real-time, creating a closed-loop system that improves phase noise performance without requiring additional power-consuming hardware components.
Solution Approach 2:
The patent replaces potential hardware-based quantization error correction mechanisms with a software/digital estimation algorithm. Instead of using additional analog-to-digital converters or complex digital circuitry to physically correct quantization errors, the system uses computational estimation techniques that process existing digital signals to generate error corrections, thereby avoiding additional power consumption associated with extra hardware components.
2Measurement precision
If quantization error mitigation techniques are applied to improve phase noise performance, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The estimator component serves multiple functions within the DPLL system: it quantizes phase differences, estimates quantization errors, generates correction values, and feeds back corrected phase measurements. This multi-functional approach eliminates the need for separate dedicated components for each function, thereby improving phase noise performance without proportionally increasing device complexity.
Solution Approach 2:
The patent introduces an intermediary estimator component that acts as a mediator between the TDC and the control loop. This intermediary processes quantized phase values and generates error corrections without requiring direct modification of the existing TDC or control loop architecture, thereby simplifying integration and reducing overall device complexity while still achieving improved phase noise performance.
3Measurement precision
If a-priori probability phase estimation is used to reduce quantization noise, then phase measurement precision is improved, but computational complexity increases
Solution Approach 1:
The patent applies preliminary action by using a-priori knowledge of the TDC's quantization characteristics to pre-calculate probability distributions and expected error values. These pre-computed statistical parameters are stored and readily available when phase measurements need correction, avoiding the need for complex real-time calculations and reducing computational complexity while maintaining high measurement precision.
Solution Approach 2:
The patent transforms the complex problem of continuous phase error correction into a discrete parameter-based solution. By representing quantization errors as discrete probability distributions with specific parameters (mean, variance) based on a-priori TDC characteristics, the system simplifies the computational complexity from continuous optimization to parameter lookup and application, thereby improving phase measurement precision without excessive computational burden.
Data Source
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AI summary
A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the unquantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.