Digital Subsampling PLL for Interference-Robust Phase Lock
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Solution Overview
Problem
Existing Phase Locked Loop (PLL) circuits with subsampling phase detectors achieve high performance in terms of phase noise versus power consumption but are sensitive to interference, leading to potential loss of lock in applications with high reliability requirements.
Innovation Solution
A PLL circuit with multiphase output signals that uses subsampling and digital processing to estimate phase, calculate phase differences, and accumulate these differences to generate a control signal for the oscillator, thereby enhancing robustness to interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If subsampling phase detectors are used in PLL circuits, then phase noise versus power consumption performance is improved, but robustness to interference deteriorates
Solution Approach 1:
The patent replaces the traditional analog subsampling phase detector with a digital phase estimation system. The analog sampled signals are converted to digital samples via ADC, and phase is estimated using digital signal processing (calculating arctan of I/Q samples). This substitution of digital processing for analog detection maintains the low power advantage while improving robustness through digital resilience to interference.
Solution Approach 2:
The patent introduces an intermediary digital processing stage between the analog sampling and the PLL control. The digital phase estimator acts as a mediator that processes the sampled signals, calculating phase information in the digital domain. This intermediary layer provides robustness against interference while maintaining the energy efficiency of the subsampling architecture.
2Device complexity
If traditional analog PLLs are used, then design complexity is reduced and phase noise performance is excellent, but flexibility for digital algorithms is lost
Solution Approach 1:
The patent segments the PLL into distinct digital and analog portions. The phase detection and processing functions are separated into a digital domain (ADC, digital phase estimator with arctan calculation), while the frequency synthesis remains analog (VCO, loop filter). This segmentation allows digital algorithms to be applied for phase estimation while maintaining analog performance characteristics.
Solution Approach 2:
The patent changes the operating domain of the phase detector from analog to digital. By sampling the VCO output and processing in the digital domain, the system can implement various digital algorithms for phase estimation, frequency synthesis, and control while maintaining the fundamental PLL operation. This parameter change enables flexibility without sacrificing analog performance.
3Adaptability or versatility
If digital PLLs are used, then flexibility for digital algorithms is improved and analog loop filter area is reduced, but design complexity increases
Solution Approach 1:
The patent extracts the complex digital processing functions into a separate phase estimation module. The digital phase estimator, which calculates phase using arctan of I/Q samples, is isolated as a distinct functional block. This extraction allows the digital algorithms to be implemented independently, managing design complexity through modular organization while maintaining flexibility.
Data Source
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AI summary
A Phase Locked Loop PLL circuit (100) and method therein for generating multiphase output signals are disclosed. The PLL circuit (100) comprises a digitally controlled oscillator (110), a sample circuit (120), an analog to digital converter (130) and a digital processing unit (140). The digital processing unit (140) comprises a phase estimator (142) configured to estimate a phase of the multiphase output signals, a differentiator (144) configured to calculate a phase difference between a current phase and a previous phase, and an accumulator (146) configured to accumulate the phase differences generated by the differentiator (144). The PLL circuit (100) further comprises a loop filter (150) configured to receive an output from the accumulator (146) and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator (110) generating the multiphase output signals.